ACE5372

Low Power Real-Time Clock (RTC)

VER 1.3

13

Either the 12-hour or 24-hour time display system should be selected before writing time data.

ADJ

±30 Second Adjust Bit

ADJ

Description

0

Ordinary operation

1

Second digit adjustment

* The following operations are performed by setting the second ADJ bit to 1

1)

For second digits ranging from “00” to “29” seconds：Time counters smaller than seconds are reset

and second digits are set to “00”.

2)

For second digits ranging from “30” to “59” seconds: Time counters smaller than seconds are reset

and second digits are set to “00”. Minute digits are incremented by 1.

* Second digits are adjusted within 122us(within 125us: when 32KHz crystal is used) from writing

operation to ADJ.

The ADJ bit is for write only and allows no read operation.

XSTP

Oscillator Halt Sending Bit

XSTP

Description

Operation

0

Ordinary oscillation

1

Oscillator halt sensing

default

The XSTP bit senses the oscillator halt.

* When oscillation is halted after initial power on from 0V or drop in supply vo

ltage the bit is set to “1” and

which remains to be “1” after it is restarted. This bit may be used to judge validity of clock and calendar

count data after power on or supply voltage drop.

*

When this bit is set to “1”,

XSL，F6 to F0，CT2，CT1，CT0，AALE，BALE，SL2，SL1，CLEN and

TEST bits are reset to “0”.

INTRA will stop output and the INTRB will output 32KHz clock pulses.

The XSTP bit is set to “0” by setting the control register 2 (address FH) during ordinary oscillation.

CLEN

32KHz Clock Output Bit

CLEN

Description

Operation

0

32KHz clock output enabled

Default

1

32KHz clock output disabled

By setting this bit to “0”, output of clock pulses of the same frequency as the crystal oscillator is enabled.

CTFG

Periodic Interrupt Flag Bit

CTFG

Description

Operation

0

Periodic interrupt output=OFF

Default

1

Periodic interrupt output=ON