AD526

REV. D

–13–

HIGH ACCURACY A/D CONVERTERS

Very high accuracy and high resolution floating-point A/D con-

verters can be achieved by the incorporation of offset and gain

calibration routines. There are two techniques commonly used

for calibration, a hardware circuit as shown in Figure 43 and/or

a software routine. In this application the microprocessor is

functioning as the autoranging circuit, requiring software over-

head; therefore, a hardware calibration technique was applied

which reduces the software burden. The software is used to set

the gain of the AD526. In operation the signal is converted, and

if the MSB of the AD574 is not equal to a Logical 1, the gain is

increased by binary steps, up to the maximum gain. This maxi-

mizes the full-scale range of the conversion process and insures

a wide dynamic range.

The calibration technique uses two point correction, offset and

gain. The hardware is simplified by the use of programmable

magnitude comparators, the 74ALS528s, which can be “burned”

for a particular code. In order to prevent under or over range

hunting during the calibration process, the reference offset and

gain codes should be different from the endpoint codes. A cali-

bration cycle consists of selecting whether gain or offset is to be

calibrated then selecting the appropriate multiplexer channel to

apply the reference voltage to the signal channel. Once the op-

eration has been initiated, the counter, a 74ALS869, drives the

D/A converter in a linear fashion providing a small correction

voltage to either the gain or offset trim point of the AD574. The

output of the A/D converter is then compared to the value pre-

set in the 74ALS528 to determine a match. Once a match is

detected, the 74ALS528 produces a low going pulse which stops

the counter. The code at the D/A converter is latched until the

next calibration cycle. Calibration cycles are under the control

of the microprocessor in this application and should be imple-

mented only during periods of converter inactivity.

A2

A1

A4

A3

AD588

NOISE

REDUCTION

R8

R1

R2

R3

R4

R5

R6

1 F

–5V

+5V

+15V

–15V

SYS

GND

0.1 F

0.1 F

AD7501

DECODED

ADDRESS

AD526

DECODED

ADDRESS

WR

WR

ADDRESS BUS

10k

–15V +15V

AD585

–15V +15V

200pF

F

S

21

7404

OP27

+15V

–15V

DE-

CODED

ADD

WR

+

+

+15V

–15V

+5V

10 F

10 F

MSB

LSB

+5V

50k

1k

AD574

DATA

BUS

12

12

MSB

LSB

74ALS

528

GAIN

P = Q

+5V

MSB

LSB

74ALS

528

OFFSET

P = Q

+5V

7475

7475

1/2

+5V

+5V

7475

1/2

7400

1

3

2

7400

6

4

5

PIN 28

AD574

ADG221

CONTROL

LOGIC

INPUT

BUFFER

LATCH

DAC A

LATCH

DAC B

AD7628

WR

A/B

WR

74ALS

869

MSB

LSB

CALIBRATION

PRESET

VALUE

+5V

+5V

5k

RFB A

RFB A

RFB A

RFB B

A1

OUT A

AD712

10k

A2

AD712

20k

PIN 15

AD588

R5

20k

R11

5k

A3

OUT B

AD712

AGND

AGND

10k

20k

PIN 15

AD588

A2

AD712

R8

20k

R12

5k

AGND

OFFSET

GAIN

NOTE: ALL BYPASS CAPACITORS ARE 0.1 F

Figure 43. High Accuracy A/D Converter