REV. 0

–2–

AD6600–SPECIFICATIONS

DC SPECIFICATIONS

Test

AD6600AST

Parameter

Temp

Level

Min

Typ

Max

Unit

ANALOG INPUTS (AIN,

AIN/BIN, BIN)

Full

V

2.0

V p-p

Differential Analog Input Resistance

2

Full

IV

160

200

240

Ω

Differential Analog Input Capacitance

25

°C

V

1.5

pF

PEAK DETECTOR (Internal), RSSI

Resolution

3

Bits

RSSI Gain Step

Full

V

6

dB

RSSI Hysteresis

3

Full

V

6

dB

RESONANT PORT (FLT,

FLT)

Differential Port Resistance

Full

V

630

Ω

Differential Port Capacitance

Full

V

1.75

pF

A/D CONVERTER

Resolution

Full

IV

11

Bits

ENCODE INPUTS (ENC,

ENC)

Differential Input Voltage (AC-Coupled)

4

Full

IV

0.4

V p-p

Differential Input Resistance

25

°CV

11

k

Ω

Differential Input Capacitance

25

°C

V

2.5

pF

A/B MODE INPUTS (A_SEL, B_SEL)

5

Input High Voltage Range

Full

IV

4.75

5.25

V

Input Low Voltage Range

Full

IV

0.0

0.5

V

POWER SUPPLY

Supply Voltages

AVCC

Full

II

4.75

5.0

5.25

V

DVCC

Full

IV

3.0

3.3

5.25

V

Supply Current

Full

II

145

182

mA

Full

II

15

20

mA

POWER CONSUMPTION

6

Full

II

775

976

mW

NOTES

Specifications subject to change without notice.

DIGITAL SPECIFICATIONS

Test

AD6600AST

Parameter

Temp

Level

Min

Typ

Max

Unit

LOGIC OUTPUTS (D10–D0, AB_OUT, RSSI2–0)

1

Logic Compatibility

CMOS

Logic “1” Voltage (DVCC = 3.3 V)

Full

II

2.8

DVCC – 0.2

V

Logic “0” Voltage (DVCC = 3.3 V)

Full

II

0.2

0.5

V

Logic “1” Voltage (DVCC = 5.0 V)

Full

IV

4.0

DVCC – 0.35

V

Logic “0” Voltage (DVCC = 5.0 V)

Full

IV

0.35

0.5

V

Output Coding (D10–D0)

Two’s Complement

CLK2

Logic “1” Voltage (DVCC = 3.3 V)

Full

II

2.8

DVCC – 0.2

V

Logic “0” Voltage (DVCC = 3.3 V)

Full

II

0.2

0.5

V

Logic “1” Voltage (DVCC = 5.0 V)

Full

IV

4.0

DVCC – 0.3

V

Logic “0” Voltage (DVCC = 5.0 V)

Full

IV

0.35

0.5

V

NOTES

× output voltage levels, high and low, tested at switching rate of 10 MHz.

Specifications subject to change without notice.