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AD6620S/PCB データシート(PDF) 5 Page - Analog Devices |
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AD6620S/PCB データシート(HTML) 5 Page - Analog Devices |
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5 / 43 page  AD6620 –5– REV. 0 TIMING CHARACTERISTICS (C LOAD = 40 pF All Outputs) Test AD6620AS Parameter (Conditions) Temp Level Min Typ Max Units CLK Timing Requirements: tCLK CLK Period Full I 15.4 ns tCLKL CLK Width Low Full IV 7.0 0.5 × t CLK ns tCLKH CLK Width High Full IV 7.0 0.5 × t CLK ns Reset Timing Requirements: tRESL RESET Width Low Full I 30.0 ns Input Data Timing Requirements: tSI Input 1 to CLK Setup Time Full IV –1.0 ns tHI Input 1 to CLK Hold Time Full IV 6.5 ns Parallel Output Switching Characteristics: tDPR CLK to OUT[15:0] Rise Delay Full IV 8.0 19.5 ns tDPF CLK to OUT[15:0] Fall Delay Full IV 7.5 19.5 ns tDPR CLK to DVOUT Rise Delay Full IV 6.5 19.0 ns tDPF CLK to DVOUT Fall Delay Full IV 5.5 11.5 ns tDPR CLK to IQOUT Rise Delay Full IV 7.0 19.5 ns tDPF CLK to IQOUT Fall Delay Full IV 6.0 13.5 ns tDPR CLK to ABOUT Rise Delay Full IV 7.0 19.5 ns tDPF CLK to ABOUT Fall Delay Full IV 5.5 13.5 ns SYNC Timing Requirements: tSY SYNC 2 to CLK Setup Time Full IV –1.0 ns tHY SYNC 2 to CLK Hold Time Full IV 6.5 ns SYNC Switching Characteristics: tDY CLK to SYNC 3 Delay Time Full V 7.0 23.5 ns Serial Input Timing: tSSI SDI to SCLK t Setup Time Full IV 1.0 ns tHSI SDI to SCLK t Hold Time Full IV 2.0 ns tHSRF SDFS to SCLK u Hold Time Full IV 4.0 ns tSSF SDFS to SCLK t Setup Time 4 Full IV 1.0 ns tHSF SDFS to SCLK t Hold Time 4 Full IV 2.0 ns Serial Frame Output Timing: tDSE SCLK u to SDFE Delay Time Full IV 3.5 11.0 ns tSDFEH SDFE Width High Full V tSCLK ns tDSO SCLK u to SDO Delay Time Full IV 4.5 11.0 ns SCLK Switching Characteristics, SBM = “1”: tSCLK SCLK Period3 Full I 2 × t CLK ns tSCLKL SCLK Width Low Full V 0.5 × t SCLK ns tSCLKH SCLK Width High Full V 0.5 × t SCLK ns tSCLKD CLK to SCLK Delay Time Full V 6.5 13.0 ns Serial Frame Timing, SBM = “1”: tDSF SCLK u to SDFS Delay Time Full IV 1.0 4.0 ns tSDFSH SDFS Width High Full V tSCLK ns SCLK Timing Requirements, SBM = “0”: tSCLK SCLK Period Full I 15.4 ns tSCLKL SCLK Width Low Full IV 0.4 × t SCLK 0.5 × t SCLK ns tSCLKH SCLK Width High Full IV 0.4 × t SCLK 0.5 × t SCLK ns NOTES 1Specification pertains to: IN[15:0], EXP[2:0], A/B. 2Specification pertains to: SYNC_NCO, SYNC_CIC, SYNC_RCF. 3SCLK period will be ≥ 2 × t CLK when AD6620 is Serial Bus Master (SBM = 1) depending on the SDIV word. 4SDFS setup and hold time must be met, even when configured as outputs, since internally the signal is sampled at the pad. Specifications subject to change without notice. |
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