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AD6623BC/PCB データシート(PDF) 6 Page - Analog Devices

部品番号 AD6623BC/PCB
部品情報  4-Channel, 104 MSPS Digital Transmit Signal Processor TSP
PDF  40 Pages
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メーカー  AD [Analog Devices]
ホームページ  http://www.analog.com
Logo AD - Analog Devices

AD6623BC/PCB データシート(HTML) 6 Page - Analog Devices

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REV. 0
–6–
AD6623
MICROPROCESSOR PORT TIMING CHARACTERISTICS1, 2
Test
AD6623AS
Parameter (Conditions)
Temp
Level
Min
Typ
Max
Unit
MICROPROCESSOR PORT, MODE INM (MODE = 0)
MODE INM Write Timing:
tSC
Control
3 to
↑CLK Setup Time
Full
IV
4.5
ns
tHC
Control
3 to
↑CLK Hold Time
Full
IV
2.0
ns
tHWR
WR(RW) to RDY(DTACK) Hold Time
Full
IV
8.0
ns
tSAM
Address/Data to
WR(RW) Setup Time
Full
IV
3.0
ns
tHAM
Address/Data to RDY(
DTACK) Hold Time
Full
IV
2.0
ns
tDRDY
WR(RW) to RDY(DTACK) Delay
Full
IV
4.0
ns
tACC
WR(RW) to RDY(DTACK) High Delay
Full
IV
4
× tCLK 5 × tCLK 9 × tCLK
ns
MODE INM Read Timing:
tSC
Control3 to
↑CLK Setup Time
Full
IV
4.5
ns
tHC
Control
3 to
↑CLK Hold Time
Full
IV
2.0
ns
tSAM
Address to
RD(DS) Setup Time
Full
IV
3.0
ns
tHAM
Address to Data Hold Time
Full
IV
2.0
ns
tZOZ
Data Three-State Delay
Full
IV
ns
tDD
RDY(
DTACK) to Data Delay
Full
IV
ns
tDRDY
RD(DS) to RDY(DTACK) Delay
Full
IV
4.0
ns
tACC
RD(DS) to RDY(DTACK) High Delay
Full
IV
8
× tCLK 10 × tCLK 13 × tCLK
ns
MICROPROCESSOR PORT, MOTOROLA (MODE = 1)
MODE MNM Write Timing:
tSC
Control
3 to
↑CLK Setup Time
Full
IV
4.5
ns
tHC
Control
3 to
↑CLK Hold Time
Full
IV
2.0
ns
tHDS
DS(RD) to DTACK(RDY) Hold Time
Full
IV
8.0
ns
tHRW
RW(
WR) to DTACK(RDY) Hold Time
Full
IV
8.0
ns
tSAM
Address/Data to RW(
WR) Setup Time
Full
IV
3.0
ns
tHAM
Address/Data to RW(
WR) Hold Time
Full
IV
2.0
ns
tDDTACK
DS(RD) to DTACK(RDY) Delay
ns
tACC
RW(
WR) to DTACK(RDY) Low Delay
Full
IV
4
× tCLK 5 × tCLK 9 × tCLK
ns
MODE MNM Read Timing:
tSC
Control
3 to
↑CLK Setup Time
Full
IV
4.0
ns
tHC
Control3 to
↑CLK Hold Time
Full
IV
2.0
ns
tHDS
DS(RD) to DTACK(RDY) Hold Time
Full
IV
8.0
ns
tSAM
Address to
DS(RD) Setup Time
Full
IV
3.0
ns
tHAM
Address to Data Hold Time
Full
IV
2.0
ns
tZD
Data Three-State Delay
Full
IV
ns
tDD
DTACK(RDY) to Data Delay
Full
IV
ns
tDDTACK
DS(RD) to DTACK(RDY) Delay
Full
IV
ns
tACC
DS(RD) to DTACK(RDY) Low Delay
Full
IV
8
× tCLK 10 × tCLK 13 × tCLK
ns
NOTES
1All Timing Specifications valid over VDD range of 2.375 V to 2.675 V and VDDIO range of 3.0 V to 3.6 V.
2C
LOAD = 40 pF on all outputs (unless otherwise specified).
3Specification pertains to control signals: RW, (
WR), DS, (RD), CS.
Specifications subject to change without notice.



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