AD7302

–3–

REV. 0

Parameter

(B Version)

Units

Conditions/Comments

0

ns min

Address to Write Setup Time

0

ns min

Address Valid to Write Hold Time

0

ns min

Chip Select to Write Setup Time

0

ns min

Chip Select to Write Hold Time

20

ns min

Write Pulse Width

15

ns min

Data Setup Time

4.5

ns min

Data Hold Time

20

ns min

Write to

LDAC Setup Time

20

ns min

LDAC Pulse Width

20

ns min

CLR Pulse Width

NOTES

°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of V

A/B

CS

WR

D7–D0

LDAC

CLR

Figure 1. Timing Diagram for Parallel Data Write