AD73322AST datasheet(9/43 Pages) AD

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AD73322

–9–

REV. B

TIMING CHARACTERISTICS

Limit at

Parameter

TA = –40 C to +85 C

Units

Description

Clock Signals

See Figure 1

ns min

MCLK Period

24.4

ns min

MCLK Width High

24.4

ns min

MCLK Width Low

Serial Port

See Figures 3 and 4

ns min

SCLK Period

0.4

× t

ns min

SCLK Width High

0.4

× t

ns min

SCLK Width Low

ns typ

SDI/SDIFS Setup Before SCLK Low

ns typ

SDI/SDIFS Hold After SCLK Low

ns typ

SDOFS Delay from SCLK High

t10

ns typ

SDOFS Hold After SCLK High

t11

ns typ

SDO Hold After SCLK High

t12

ns typ

SDO Delay from SCLK High

t13

ns typ

SCLK Delay from MCLK

Specifications subject to change without notice.

(AVDD = +5 V

10%; DVDD = +5 V

10%; AGND = DGND = 0 V; TA = TMlN to TMAX, unless

otherwise noted)

Figure 1. MCLK Timing

t11

t10

SE (I)

SCLK (O)

SDIFS (I)

SDI (I)

SDOFS (O)

SDO (O)

THREE-

STATE

THREE-

STATE

THREE-

STATE

D15

D2D1D0

D14

D15

D14

D15

t12

Figure 4. Serial Port (SPORT)

t13

* SCLK IS INDIVIDUALLY PROGRAMMABLE

IN FREQUENCY (MCLK/4 SHOWN HERE).

MCLK

SCLK*

Figure 3. SCLK Timing

TO OUTPUT

+2.1V

100 A

IOL

IOH

15pF

Figure 2. Load Circuit for Timing Specifications

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