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AD7476SRTZ-R2 データシート(PDF) 17 Page - Analog Devices

部品番号 AD7476SRTZ-R2
部品情報  1 MSPS, 12-/10-/8-Bit ADCs in 6-Lead SOT-23
PDF  20 Pages
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メーカー  AD [Analog Devices]
ホームページ  http://www.analog.com
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AD7476SRTZ-R2 データシート(HTML) 17 Page - Analog Devices

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REV. D
AD7476/AD7477/AD7478
–17–
AD7476/AD7477/AD7478 to DSP56xxx Interface
The connection diagram in Figure 20 shows how the AD7476/
AD7477/AD7478 can be connected to the SSI (Synchronous
Serial Interface) of the DSP56xxx family of DSPs from Motorola.
The SSI is operated in Synchronous Mode (SYN bit in
CRB =1) with internally generated word frame sync for both
Tx and Rx (Bits FSL1 = 0 and FSL0 = 0 in CRB). Set the word
length to 16 by setting bits WL1 = 1 and WL0 = 0 in CRA. To
implement the Power-Down mode on the AD7476/AD7477/
AD7478, the word length can be changed to eight bits by setting
bits WL1 = 0 and WL0 = 0 in CRA. It should be noted that
for signal processing applications, it is imperative that the
frame synchronization signal from the DSP56xxx provides
equidistant sampling.
SDATA
CS
SRD
SC2
AD7476/
AD7477/
AD7478*
SCLK
DSP56xxx*
SCK
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 20. Interfacing to the DSP56xxx
AD7476/AD7477/AD7478 to MC68HC16 Interface
The Serial Peripheral Interface (SPI) on the MC68HC16 is
configured for Master Mode (MSTR = 1), the Clock Polarity
Bit (CPOL) = 1, and the Clock Phase Bit (CPHA) = 0. The SPI
is configured by writing to the SPI Control Register (SPCR)—see
the 68HC16 User Manual. The serial transfer will take place as
a 16-bit operation when the SIZE bit in the SPCR register is set
to SIZE = 1. To implement the Power-Down mode with an
8-bit transfer, set SIZE = 0. A connection diagram is shown
in Figure 21.
SDATA
CS
MISO/PMC0
SS/PMC3
AD7476/
AD7477/
AD7478*
SCLK
MC68HC16*
SCLK/PMC2
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 21. Interfacing to the MC68HC16



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