REV. 0

AD7675

–13–

Care should also be taken with the reference temperature coeffi-

cient of the voltage reference which directly affects the full-scale

accuracy if this parameter matters. For instance, a

±15 ppm/°C

tempco of the reference changes the full scale by

±1 LSB/°C.

to AVDD – 1.85 V. The benefit here is the increased SNR

obtained as a result of this increase. Since the input range is

range to make it a

± 3 V input range with an AVDD above

4.85 V. The theoretical improvement as a result of this increase

in reference is 1.58 dB (20 log [3/2.5]). Due to the theoretical

quantization noise, however, the observed improvement is

approximately 1 dB. The AD780 can be selected with a 3 V

reference voltage.

Power Supply

The AD7675 uses three sets of power supply pins: an analog

5 V supply AVDD, a digital 5 V core supply DVDD, and a

digital input/output interface supply OVDD. The OVDD supply

allows direct interface with any logic working between 2.7 V and

5.25 V. To reduce the number of supplies needed, the digital

core (DVDD) can be supplied through a simple RC filter from

the analog supply as shown in Figure 5. The AD7675 is inde-

pendent of power supply sequencing and thus free from supply

voltage induced latchup. Additionally, it is very insensitive to

power supply variations over a wide frequency range as shown

in Figure 9.

FREQUENCY – Hz

75

35

65

10k

10M

1k

1M

55

100k

45

70

60

50

40

Figure 9. PSRR vs. Frequency

POWER DISSIPATION

The AD7675 automatically reduces its power consumption at

the end of each conversion phase. During the acquisition phase,

the operating currents are very low which allows a significant

power saving when the conversion rate is reduced as shown in

Figure 10. This feature makes the AD7675 ideal for very low-

power battery applications.

It should be noted that the digital interface remains active even

during the acquisition phase. To reduce the operating digital

supply currents even further, the digital inputs need to be driven

close to the power rails (i.e., DVDD and DGND) and OVDD

should not exceed DVDD by more than 0.3 V.

SAMPLING RATE – SPS

0.1

10k

100

100k

10

10k

100

1k

1

100k

1k

10

1M

Figure 10. Power Dissipation vs. Sample Rate

CONVERSION CONTROL

Figure 11 shows the detailed timing diagrams of the conversion

process. The AD7675 is controlled by the signal CNVST which

initiates conversion. Once initiated, it cannot be restarted or

aborted, even by the power-down input PD, until the conver-

sion is complete. The CNVST signal operates independently of

CS and RD signals.

CNVST

MODE

ACQUIRE

CONVERT

ACQUIRE

CONVERT

BUSY

Figure 11. Basic Conversion Timing

For true sampling applications, the recommended operation of

the CNVST signal is as follows:

CNVST must be held high from the previous falling edge of

BUSY, and during a minimum delay corresponding to the

conversion is initiated and BUSY signal goes high until the

completion of the conversion. Although CNVST is a digital

signal, it should be designed with this special care with fast,

clean edges and levels, with minimum overshoot and under-

shoot or ringing.

For applications where the SNR is critical, the CNVST signal should

have a very low jitter. Some solutions to achieve that are to use a

dedicated oscillator for CNVST generation or, at least, to clock

it with a high-frequency low-jitter clock, as shown in Figure 5.