AD7722AS datasheet(20/24 Pages) AD

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AD7722

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serial data is made available on SDO after the rising edge of

SCO and can be latched on the SCO falling edge.

The master device is selected by setting TSI to a logic low and

connecting its FSO to DOE. The slave device is selected with its

TSI pin tied high, and both its FSI and DOE are controlled

from the master’s FSO. Since the FSO of the master controls

the DOE input of both the master and slave, one ADCs SDO is

active while the other is high impedance (Figure 40). When the

master transmits its conversion result during the first 16 SCO

cycles of a data transmission frame, the low level on DOE sets

the slave’s SDO high impedance. Once the master completes

transmitting its conversion data, its FSO goes high and triggers

the slave’s FSI to begin its data transmission frame.

Serial Interfacing to DSPs

In serial mode, the AD7722 can be interfaced directly to several

industry standard DSPs. In all cases, the AD7722 operates as

the master with the DSP operating as the slave. The AD7722

outputs its own serial clock (SCO) to transmit the digital word

on the SDO pin to a DSP. The DSP’s serial interface is synchro-

nized to the data transmission provided by the FSO signal.

Since the serial data clock from the AD7722 is always one-half

the CLKIN frequency, DSPs that can accept relatively high

serial clock frequencies are required. The ADSP-21xx family of

DSPs can operate with a maximum serial clock of 13.824 MHz;

the DSP56002 allows a maximum serial clock of 13.3 MHz;

while the TMS320C5x-57 accepts a maximum serial clock of

10.989 MHz. To interface the AD7722 to other DSPs, the

master clock frequency of the AD7722 can be reduced so that

the SCO frequency equals the maximum allowable frequency of

the serial clock input to the DSP. When the AD7722 is operated

with a lower CLKIN frequency (< 10 MHz), DSPs such as the

TMS320C20/C25 and DSP56000/1 can be used.

Figures 41 to 43 show the interfaces between the AD7722 and

several DSPs. In all cases, the interface control pins, TSI, DOE,

SFMT, CFMT, SYNC, and FSI can be permanently hardwired

together to either DGND or DVDD. Alternatively, SFMT or

CFMT can be tied either high or low to configure the serial data

interface for the particular format required by the DSP. The

frame synchronization signal, FSI, can be applied from the user’s

system control logic.

FSO

SDO

SCO

AD7722

RFS

SCLK

ADSP-21xx

Figure 41. AD7722 to ADSP-21xx Interface

FSO

SDO

SCO

SC1

SRD

SCK

AD7722

DSP56001/2/3

Figure 42. AD7722 to DSP56000 Interface

FSO

SDO

SCO

FSR

CLKR

AD7722

TMS320CXX

Figure 43. AD7722 to TMS320C20/25/50 Interface

Grounding and Layout

The analog and digital power supplies to the AD7722 are

independent and separately pinned out to minimize coupling

between analog and digital sections within the device. The

AD7722 should be treated as an analog component and

grounded and decoupled to the analog ground plane. All the

AD7722 ground pins should be soldered directly to a ground

plane to minimize series inductance. All converter power pins

should be decoupled to the analog ground plane. To achieve the

best decoupling, place surface mount capacitors as close as

possible to the device, ideally right up against the device pins.

The printed circuit board that houses the AD7722 should use

separate ground planes for the analog and the digital interface

circuitry. All converter power pins should be decoupled to the

analog ground plane, and all interface logic circuit power pins

should be decoupled to the digital ground plane. This facilitates

the use of ground planes, which can physically separate sensitive

analog components from the noisy digital system. Digital and

analog ground planes should only be joined in one place and

should not overlap to minimize capacitive coupling between

them.

Separate power supplies for AVDD and DVDD are also highly

desirable. The digital supply pin DVDD should be powered

from a separate analog supply, but if necessary DVDD may

share its power connection to AVDD. Refer to the connection

diagram (Figure 44). The 10

Ω resistor, in series with the

DVDD pin, is required to dampen the effects of the fast

switching currents into the digital section of the AD7722. The

ferrite is also recommended to filter high frequency signals from

corrupting the analog power supply.

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