AD7804 datasheet(13/28 Pages) AD

13 / 28 page

AD7804/AD7805/AD7808/AD7809

–13–

REV. A

DB9

DB0

DB9

DB8

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

X = Don’t Care

Figure 14. AD7805/AD7809 Main DAC Data Register (Top)

and Sub DAC Data Register (Bottom) Configuration

(MODE = 1,

10/8 = 0)

Figure 15 shows the bit allocations when 8-bit parallel operation

is selected in the system control register. DB9 to DB2 are re-

tained as data bits. DB1 acts as a high byte or low byte enable.

When DB1 is low, the eight MSBs of the data word are loaded

to the input register. When DB1 is high, the low byte consisting

of the two LSBs are loaded to the input register. DB0 is used to

select either the Main or Sub DAC when in the byte mode.

DB9

DB2

DB1

DB0

DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2

MAIN/SUB

XDB1 DB0

MAIN/SUB

X = Don’t Care

Figure 15. AD7805/AD7809 Main DAC Data Register Con-

figuration (MODE = 1,

10/8 = 1, MAIN/SUB = 0)

Figure 16 shows the bit allocations for writing to the Sub DAC.

DB9

DB2

DB1

DB0

DB7

DB6 DB5 DB4 DB3 DB2 DB1 DB0

MAIN/SUB

X = Don’t Care

Figure 16. AD7805/AD7809 Sub DAC Data Register Con-

figuration (MODE = 1,

MAIN/SUB = 1)

Each DAC has a separate channel control register. The follow-

ing is a brief discussion on the bits in each of the control registers.

DAC Selection (A2, A1, A0)

The external address pins in conjunction with

CS, WR and

MODE are used to address the various DAC data and control

registers. Table IVa shows how these DAC registers can be

addressed on the AD7805. Table IVb shows how these registers

are addressed on the AD7809. Refer to Figures 12 to 16 for infor-

mation on the registers.

Table IVa. AD7805 DAC Data/Control Register

Selection Table

MODE

Function Selected

DAC A Control Registers

DAC B Control Registers

DAC C Control Registers

DAC D Control Registers

DAC A Data Registers

DAC B Data Registers

DAC C Data Registers

DAC D Data Registers

of the Main DAC to the bottom of the transfer function, VBIAS/16.

With twos complement coding the output of the DAC is cleared

to midscale which is VBIAS. A hardware clear always clears the

output of the Sub DAC to midscale thus the output of the Sub

DAC makes zero contribution to the output of the channel.

D2 D1 D0

MODE ADDR

DATA REGISTER

VBIAS

INTERNAL VREF

VDD/2

REFIN

VOUT

TO ALL

CHANNELS

SINGLE

CHANNEL

DAC REGISTER

8-BIT DAC

(SUB DAC)

DATA REGISTER

DAC REGISTER

10-BIT DAC

(MAIN DAC)

CHANNEL

CONTROL

MUX

SYSTEM

CONTROL

DECODER

CONTROL

LOGIC

LDAC

INPUT REGISTER

Figure 11. AD7805/AD7809 Internal Registers

AD7805/AD7809 CONTROL REGISTERS

Access to the control registers of the AD7805/AD7809 is

achieved by taking the mode pin to a logic low. The control

There are two control registers associated with the part. System

control register which looks after the input coding, data format,

power down, system clear and system standby. The channel

control register contains bits that affect the operation of the

selected DAC. The external address bits are used to select the

DACs. These registers are eight bits wide and the last two bits

are control bits. The mode pin must be low to have access to the

control registers.

DB9

DB2 DB1

DB0

10/8 BIN/COMP PD SSTBY SCLR 0

MD0 = 0

X = Don’t Care

Figure 12. AD7805/AD7809 System Control Register Con-

figuration, (MODE = 0)

DB9

DB2

DB1

DB0

MX1 MX0

MAIN/SUB X

STBY CLR 0

MD0 = 1

X = Don’t Care

Figure 13. AD7805/AD7809 Channel Control Register Con-

figuration (MODE = 0)

The external mode pin must be taken high to allow data to be

written to the DAC data registers. Figure 14 shows the bit allo-

cations when 10-bit parallel operation is selected in the system

control register.

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