AD8303AN datasheet(3/16 Pages) AD

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SPECIFICATIONS

+5 V OPERATION

Parameter

Symbol

Condition

Min

Typ1

Max

Units

STATIC PERFORMANCE

Resolution

Bits

Relative Accuracy

INL

–2

±1/2

LSB

Differential Nonlinearity

DNL

Monotonic, TA = +25°C

–3/4

±1/4

+3/4

LSB

Differential Nonlinearity

DNL

Monotonic

–1

±1/2

LSB

Zero-Scale Error

VZSE

Data = 000H

1.25

+4.5

Full-Scale Voltage

VFS

Data = FFFH

2.039

2.0475 2.056

Volts

Full-Scale Tempco

3, 4

TCVFS

ppm/

°C

ANALOG OUTPUTS

Output Current

IOUT

Data = 800H, ∆VOUT < 3 mV

±3mA

Output Resistance to GND

ROUT

Data = 000H

Ω

Capacitive Load

No Oscillation

500

REFERENCE OUTPUT

Output Voltage

REF

Load > 1 M

Ω

LOGIC INPUTS

Logic Input Low Voltage

VIL

0.8

Logic Input High Voltage

VIH

2.4

Input Leakage Current

IIL

µA

Input Capacitance

CIL

INTERFACE TIMING SPECIFICATIONS

4, 5

Clock Width High

Clock Width Low

Load Pulse Width

LDW

Data Setup

Data Hold

Reset Pulse Width

tRS

Load Setup

tLD1

Load Hold

tLD2

Select

tCSS

Deselect

tCSH

AC CHARACTERISTICS

Voltage Output Settling Time

±0.1% of Full Scale

µs

Voltage Output Settling Time

±1 LSB of Final Value5

µs

Shutdown Recovery Time

tSDR

±0.1% of Full Scale

µs

Output Slew Rate

Data = 000H to FFFH to 000H

2V/

µs

DAC Glitch

nV s

Digital Feedthrough

nV s

SUPPLY CHARACTERISTICS

Power Supply Range

VDD RANGE DNL < ± 1 LSB

2.7

3.0

5.5

Shutdown Supply Current

IDD_SD

SHDN

= 0, No Load, VIL = 0 V, TA = +25°C

0.02

µA

Positive Supply Current

IDD

VDD = 5 V, VIL = 0 V, No Load

2.1

3.4

Power Dissipation

PDISS

VDD = 5 V, VIL = 0 V, No Load

10.5

Power Supply Sensitivity

PSS

∆V

DD = ± 10%

0.001

0.004

%/%

NOTES

1Typical readings represent the average value of room temperature operation.

21 LSB = 0.5 mV for 0 V to +2.0475 V output range. The first two codes (000

H, 001H) are excluded from the linearity error measurement.

3Includes internal voltage reference error.

4These parameters are guaranteed by design and not subject to production testing.

5All input control signals are specified with t

R = tF = 2 ns (10% to 90% of +5 V) and timed from a voltage level of 1.6 V.

6The settling time specification does not apply for negative going transitions within the last 6 LSBs of ground.

7See Figure 6 for a plot of incremental supply current consumption as a function of the digital input voltage levels.

Specifications subject to change without notice.

AD8303

REV. 0

–3–

(@ VDD = +5 V

10%, –40 C

≤ T

≤ +85 C, unless otherwise noted)

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