EM47DM0888SBA

May. 2011

32/39

www.eorex.com

Burst Type (A3)

Burst Length

R/W

A2

A1

A0

Sequential Addressing, A3=0

Interleave Addressing, A3=1

R

0

0

0

0 1 2 3 T T T T

0 1 2 3 T T T T

R

0

0

1

1 2 3 0 T T T T

1 0 3 2 T T T T

R

0

1

0

2 3 0 1 T T T T

2 3 0 1 T T T T

R

0

1

1

3 0 1 2 T T T T

3 2 1 0 T T T T

R

1

0

0

4 5 6 7 T T T T

4 5 6 7 T T T T

R

1

0

1

5 6 7 4 T T T T

5 4 7 6 T T T T

R

1

1

0

6 7 4 5 T T T T

6 7 4 5 T T T T

R

1

1

1

7 4 5 6 T T T T

7 6 5 4 T T T T

W

0

V

V

0 1 2 3 X X X X

0 1 2 3 X X X X

4 (chop)

W

1

V

V

4 5 6 7 X X X X

4 5 6 7 X X X X

R

0

0

0

0 1 2 3 4 5 6 7

0 1 2 3 4 5 6 7

R

0

0

1

1 2 3 0 5 6 7 4

1 0 3 2 5 4 7 6

R

0

1

0

2 3 0 1 6 7 4 5

2 3 0 1 6 7 4 5

R

0

1

1

3 0 1 2 7 4 5 6

3 2 1 0 7 6 5 4

R

1

0

0

4 5 6 7 0 1 2 3

4 5 6 7 0 1 2 3

R

1

0

1

5 6 7 4 1 2 3 0

5 4 7 6 1 0 3 2

R

1

1

0

6 7 4 5 2 3 0 1

6 7 4 5 2 3 0 1

R

1

1

1

7 4 5 6 3 0 1 2

7 6 5 4 3 2 1 0

8

W

V

V

V

0 1 2 3 4 5 6 7

0 1 2 3 4 5 6 7

Note1.

In case of burst length being fixed to 4 by MR0 setting, the internal write operation starts two clock

cycles earlier than for the BL8 mode. This means that the starting point for tWR and tWTR will be pulled

in by two clocks. In case of burst length being selected on-the-fly via A12 (/BC), the internal write

operation starts at the same point in time like a burst of 8 write operation. This means that during

on-the-fly control, the starting point for tWR and tWTR will not be pulled in by two clocks.

Note2.

0...7 bit number is value of CA[2:0] that causes this bit to be the first read during a burst.

Note3.

T: Output driver for data and strobes are in high impedance.

Note4.

V: a valid logic level (0 or 1), but respective buffer input ignores level on input pins.

Note5.

X: Don’t Care.