AD9483SLASHPCB datasheet(7/26 Pages) AD

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AD9483

–7–

REV. A

TIMING

AIN

ENCODE

D7–D0

CLOCK OUT

SAMPLE N–1

SAMPLE N

SAMPLE N+3

SAMPLE N+4

SAMPLE N+2

SAMPLE N+1

tEH

tEL

1/fS

DATA N–5

DATA N–4

DATA N–3

DATA N–2

DATA N–1

DATA N

tCPD

tPD

tCV

Figure 1. Timing—Single Channel Mode

tCPD

tEH

tEL

1/fS

INTERLEAVED DATA OUT

SAMPLE N–2

ENCODE

CLKOUT

SAMPLE N+1

SAMPLE N

SAMPLE N+3

SAMPLE N+4

SAMPLE N–1

DATA N–3

DATA N–2

DATA N–1

DATA N

tPD

DATA N–2

PORT B

D7–D0

PORT A

D7–D0

PORT B

D7–D0

PORT A

D7–D0

AIN

tHDS

tSDS

SAMPLE N+5

SAMPLE N+6

INVALID IF OUT OF SYNC

DATA N–4 IF IN SYNC

INVALID IF OUT OF SYNC

DATA N–5 IF IN SYNC

INVALID IF OUT OF SYNC

DATA N–4 IF IN SYNC

INVALID IF OUT OF SYNC

DATA N–5 IF IN SYNC

DATA N–7

OR N–6

DATA N–7

OR N–8

DATA N–6

OR N–7

DATA N–8

OR N–7

DATA N–8

OR N–7

DATA N–6

OR N–7

DATA N–9

OR N–8

DATA N–7

OR N–8

DATA N–7

OR N–6

DATA N–3

DATA N–1

DATA N+1

DATA N

DATA N+1

SAMPLE N+2

PARALLEL DATA OUT

tCV

Figure 2. Timing—Dual Channel Mode

AD9483/PCB データシート(PDF) 7 Page - Analog Devices

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AD9483/PCB データシート(PDF) 7 Page - Analog Devices

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