AD9765AST datasheet(13/28 Pages) AD

13 / 28 page

REV. B

AD9765

–13–

Note that the clock input could also be driven via a sine wave,

which is centered around the digital threshold (i.e., DVDD/2)

and meets the min/max logic threshold. This will typically result

in a slight degradation in the phase noise, which becomes more

noticeable at higher sampling rates and output frequencies.

Also, at higher sampling rates, the 20% tolerance of the digital

logic threshold should be considered since it will affect the effec-

tive clock duty cycle and, subsequently, cut into the required

data setup and hold times.

DVDD

DIGITAL

INPUT

Figure 28. Equivalent Digital Input

INPUT CLOCK AND DATA TIMING RELATIONSHIP

SNR in a DAC is dependent on the relationship between the

position of the clock edges and the point in time at which the

input data changes. The AD9765 is rising edge triggered, and so

exhibits SNR sensitivity when the data transition is close to this

edge. In general, the goal when applying the AD9765 is to make

the data transition close to the falling clock edge. This becomes

more important as the sample rate increases. Figure 29 shows

the relationship of SNR to clock placement with different sample

rates. Note that at the lower sample rates, much more tolerance

is allowed in clock placement, while much more care must be

taken at higher rates.

TIME OF DATA CHANGE RELATIVE TO

RISING CLOCK EDGE – ns

–4

–2

–3

–1

Figure 29. SNR vs. Clock Placement @ fOUT = 20 MHz and

fCLK = 125 MSPS

SLEEP MODE OPERATION

The AD9765 has a power-down function that turns off the output

current and reduces the supply current to less than 8.5 mA

over the specified supply range of 3.0 V to 5.5 V and tempera-

ture range. This mode can be activated by applying a Logic

Level “1” to the SLEEP pin. The SLEEP pin logic threshold is

equal to 0.5

× AVDD. This digital input also contains an active

pull-down circuit that ensures the AD9765 remains enabled if

this input is left disconnected. The AD9765 takes less than

50 ns to power down and approximately 5

µs to power back up.

POWER DISSIPATION

The power dissipation, PD, of the AD9765 is dependent on

several factors that include: (1) The power supply voltages

(AVDD and DVDD), (2) the full-scale current output IOUTFS,

(3) the update rate fCLOCK, (4) and the reconstructed digital

input waveform. The power dissipation is directly proportional

to the analog supply current, IAVDD, and the digital supply cur-

rent, IDVDD. IAVDD is directly proportional to IOUTFS as shown

in Figure 30 and is insensitive to fCLOCK.

IOUTFS

Figure 30. IAVDD vs. IOUTFS

Conversely, IDVDD is dependent on both the digital input wave-

form, fCLOCK, and digital supply DVDD. Figures 31 and 32

show IDVDD as a function of full-scale sine wave output ratios

(fOUT/fCLOCK) for various update rates with DVDD = 5 V and

DVDD = 3 V, respectively. Note how IDVDD is reduced by more

than a factor of 2 when DVDD is reduced from 5 V to 3 V.

RATIO – fOUT/fCLK

0.10

0.20

0.30

0.40

0.50

125MSPS

100MSPS

65MSPS

25MSPS

5MSPS

Figure 31. IDVDD vs. Ratio @ DVDD = 5 V

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