AD9772AST datasheet(4/30 Pages) AD

4 / 30 page

REV. 0

–4–

AD9772–SPECIFICATIONS

DIGITAL SPECIFICATIONS

(TMIN to TMAX, AVDD = +3 V, CLKVDD = +3 V, PLLVDD = +0 V, DVDD = +3 V, IOUTFS = 20 mA, unless

otherwise noted)

Parameter

Min

Typ

Max

Units

DIGITAL INPUTS

Logic “1” Voltage

2.1

Logic “0” Voltage

0.9

Logic “1” Current

–10

+10

µA

Logic “0” Current

–10

+10

µA

Input Capacitance

CLOCK INPUTS

Input Voltage Range

Common-Mode Voltage

0.75

1.5

2.25

Differential Voltage

0.5

1.5

PLL CLOCK ENABLED—FIGURE 1a

Input Setup Time (tS)

1.0

Input Hold Time (tH)

2.5

Latch Pulsewidth (tLPW)

1.5

PLL CLOCK DISABLED—FIGURE 1b

Input Setup Time (tS)

1.0

Input Hold Time (tH)

2.5

Latch Pulsewidth (tLPW)

1.5

CLK/PLLLOCK Delay (tOD)

NOTES

1MOD1 and MOD0 have typical input currents of 120

µA while SLEEP has a typical input current of 15 µA.

Specifications subject to change without notice.

0.025%

DB0–DB13

CLK+ – CLK–

IOUTA

IOUTB

tLPW

tPD

tST

Figure 1a. Timing Diagram—PLL Clock Multiplier Enabled

DB0–DB13

0.025%

IOUTA

IOUTB

tOD

PLLLOCK

CLK+ – CLK–

tLPW

tPD

tST

Figure 1b. Timing Diagram—PLL Clock Multiplier Disabled

AD9772AST データシート(PDF) 4 Page - Analog Devices

AD9772AST データシート(HTML) 4 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30

データシートダウンロード