AD9774EB datasheet(3/24 Pages) AD

3 / 24 page

–3–

REV. B

AD9774

DYNAMIC SPECIFICATIONS

Parameter

Min

Typ

Max

Units

DYNAMIC PERFORMANCE

Maximum Output Update Rate w/DVDD = 5 V

128

MSPS

Maximum Output Update Rate w/DVDD = 3 V

100

128

MSPS

Output Settling Time (tST) (to 0.025%)

Output Propagation Delay (tPD)

Clocks

Glitch Impulse

pV-s

Output Rise Time (10% to 90%)

2.5

Output Fall Time (10% to 90%)

2.5

Output Noise (IOUTFS = 20 mA)

pA/

√Hz2

AC LINEARITY TO NYQUIST

Spurious-Free Dynamic Range (SFDR) to Nyquist

fCLOCK = 25 MSPS; fOUT = 1.01 MHz

0 dBFS Output

–6 dBFS Output

–12 dBFS Output

–18 dBFS Output

fCLOCK = 32 MSPS; fOUT = 1.01 MHz

fCLOCK = 32 MSPS; fOUT = 5.01 MHz

fCLOCK = 32 MSPS; fOUT = 10.01 MHz

fCLOCK = 32 MSPS; fOUT = 13.01 MHz

Total Harmonic Distortion (THD)

fCLOCK = 25 MSPS; fOUT = 1.01 MHz; 0 dBFS

–75

Signal-to-Noise Ratio (SNR)

fCLOCK = 25 MSPS; fOUT = 1.01 MHz; 0 dBFS

NOTES

1Propagation delay is delay from data input to DAC update.

2Measured single-ended into 50

Ω load.

Specifications subject to change without notice.

(TMIN to TMAX, AVDD = +5 V, PLLVDD = +5 V, DVDD = +5 V, IOUTFS = 20 mA, Differential Transformer

Coupled Output, 50

Doubly Terminated, unless otherwise noted)

DIGITAL SPECIFICATIONS

Parameter

Min

Typ

Max

Units

DIGITAL INPUTS

Logic “1” Voltage @ DVDD = +5 V

3.5

Logic “1” Voltage @ DVDD = +3 V

2.1

Logic “0” Voltage @ DVDD = +5 V

1.3

Logic “0” Voltage @ DVDD = +3 V

0.9

Logic “1” Current

–10

+10

µA

Logic “0” Current

–10

+10

µA

Input Capacitance

Input Setup Time (tS)

2.5

Input Hold Time (tH)

1.5

Latch Pulsewidth (tLPW)4

(TMIN to TMAX, AVDD = +5 V, PLLVDD = +5 V, DVDD = +5 V, IOUTFS = 20 mA unless otherwise noted)

0.025%

tLPW

DB0–DB11

CLOCK

IOUTA

IOUTB

Figure 1. Timing Diagram

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