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AD9822JR データシート(PDF) 2 Page - Analog Devices |
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AD9822JR データシート(HTML) 2 Page - Analog Devices |
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2 / 15 page  REV. A –2– AD9822–SPECIFICATIONS ANALOG SPECIFICATIONS Parameter Min Typ Max Unit MAXIMUM CONVERSION RATE 3-Channel Mode with CDS 15 MSPS 1-Channel Mode with CDS 12.5 MSPS ACCURACY (Entire Signal Path) ADC Resolution 14 Bits Integral Nonlinearity (INL) –17.0/+3.5 LSB INL @ 6 MHz –10.5/+1.5 LSB Differential Nonlinearity (DNL) –0.65/+0.75 LSB DNL @ 6 MHz –1.0 –0.6/+0.65 +1.1 LSB No Missing Codes 14 Bits No Missing Codes @ 6 MHz 14 Bits Offset Error –240 –19 +200 mV Gain Error –1.4 +3.5 +6.9 % FSR ANALOG INPUTS Input Signal Range 1 2.0 V p-p Allowable Reset Transient 1 1.0 V Input Limits 2 AVSS – 0.3 AVDD + 0.3 V Input Capacitance 10 pF Input Bias Current 10 nA AMPLIFIERS PGA Gain at Minimum 1 V/V PGA Gain at Maximum 5.7 V/V PGA Gain Resolution 2 64 Steps PGA Gain Monotonicity Guaranteed Programmable Offset at Minimum –350 mV Programmable Offset at Maximum +350 mV Programmable Offset Resolution 512 Steps Programmable Offset Monotonicity Guaranteed NOISE AND CROSSTALK Total Output Noise @ PGA Minimum 1.5 LSB rms Total Output Noise @ PGA Maximum 6.0 LSB rms Channel-Channel Crosstalk @ 6 MHz <1 LSB POWER SUPPLY REJECTION AVDD = +5 V ± 0.25 V 0.063 0.9 % FSR DIFFERENTIAL VREF (@ 25 °C) CAPT–CAPB (2 V ADC Full-Scale Range) 0.94 1.0 1.06 V TEMPERATURE RANGE Operating 0 +70 °C Storage –65 +150 °C POWER SUPPLIES AVDD 4.75 5.0 5.25 V DRVDD 3.0 5.0 5.25 V OPERATING CURRENT AVDD 73 mA DRVDD 4 mA Power-Down Mode Current 150 µA POWER DISSIPATION 3-Channel Mode 385 450 mW 3-Channel Mode @ 6 MHz 335 410 mW 1-Channel Mode 300 mW 1-Channel Mode @ 6 MHz 250 mW (TMIN to TMAX, AVDD = 5 V, DRVDD = 5 V, CDS Mode, fADCCLK = 15 MHz, fCDSCLK1 = fCDSCLK2 = 5 MHz, PGA Gain = 1, unless otherwise noted.) |
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