REV. 0

ADP3331

–6–

THEORY OF OPERATION

The new ADP3331 anyCAP LDO uses a single control loop for

both regulation and reference functions as shown in Figure 20.

The output voltage is sensed by an external resistive voltage

divider consisting of R1 and R2. Feedback is taken from this

network by way of a series diode (D1) and a second resistor

divider (R3 and R4) to the input of an amplifier.

PTAT

NONINVERTING

WIDEBAND

DRIVER

INPUT

Q1

ADP3331

COMPENSATION

CAPACITOR

ATTENUATION

R1

D1

R2

R3

R4

OUTPUT

PTAT

CURRENT

(a)

GND

Figure 20. Functional Block Diagram

A very high gain error amplifier is used to control this loop. The

amplifier is constructed in such a way that at equilibrium it

produces a large, temperature-proportional input “offset voltage”

that is repeatable and very well controlled. The temperature-

proportional offset voltage is combined with the complementary

diode voltage to form a “virtual bandgap” voltage, implicit in

the network, although it never appears explicitly in the circuit.

Ultimately, this patented design makes it possible to control the

loop with only one amplifier. This technique also improves the

noise characteristics of the amplifier by providing more flexibil-

ity on the trade-off of noise sources that leads to a low noise

design.

The R1, R2 divider is chosen in the same ratio as the bandgap

voltage to output voltage. Although the R1, R2 resistor divider

is loaded by the diode D1 and a second divider consisting of R3

and R4, the values are chosen to produce a temperature stable

output. This unique arrangement specifically corrects for the

loading of the divider so that the error resulting from the base

current loading in conventional circuits is avoided.

The patented amplifier controls a new and unique noninverting

driver that drives the pass transistor, Q1. The use of this special

noninverting driver enables the frequency compensation to

include the load capacitor in a pole-splitting arrangement to

achieve reduced sensitivity to the value, type and ESR of the

load capacitor.

Most LDOs place strict requirements on the range of ESR

values for the output capacitor because they are difficult to

stabilize due to the uncertainty of the load capacitance and

resistance. Moreover, the ESR value required to keep conven-

tional LDOs stable, changes depending on load and tempera-

ture. These ESR limitations make designing with LDOs more

difficult because of their unclear specifications and extreme

variations over temperature.

This is no longer true with the ADP3331. It can be used with

any good quality capacitor, with no constraint on the minimum

ESR. The innovative design allows the circuit to be stable with

just a small 0.47

µF capacitor on the output. Additional advan-

tages of the pole-splitting scheme include superior line noise

rejection and very high regulator gain. The high gain leads to

excellent regulation, and

±1.4% accuracy is guaranteed over

line, load and temperature.

Additional features of the circuit include current limit, thermal

shutdown and an error flag. Compared to standard solutions

that give a warning after the output has lost regulation, the

ADP3331 provides improved system performance by enabling

the

ERR pin to give a warning just before the device loses

regulation.

As the chip’s temperature rises above +165

°C, the circuit acti-

vates a soft thermal shutdown to reduce the current to a safe

level. The thermal shutdown condition is indicated by the

ERR

signal going low.

APPLICATION INFORMATION

Capacitor Selection

Output Capacitor: The stability and transient response of the

LDO is a function of the output capacitor. The ADP3331 is

stable with a wide range of capacitor values, types and ESR

(anyCAP). A capacitor as low as 0.47

µF is all that is needed for

stability; larger capacitors can be used if high current surges on

the output are anticipated. The ADP3331 is stable with ex-

tremely low ESR capacitors (ESR

≈ 0), such as Multilayer

Ceramic Capacitors (MLCC) or OSCON. Note that the effec-

tive capacitance of some capacitor types fall below the minimum

over temperature or with DC voltage.

Input Capacitor: An input bypass capacitor is not strictly re-

quired but it is recommended in any application involving long

input wires or high source impedance. Connecting a 0.47

µF

capacitor from the input to ground reduces the circuit’s sensitiv-

ity to PC board layout and input transients. If a larger output

capacitor is necessary, a larger value input capacitor is also

recommended.

Noise Reduction Capacitor: A noise reduction capacitor can be

used to reduce the output noise by 6 dB to 10 dB. This capaci-

tor limits the noise gain when connected between the feedback

pin (FB) and the output pin (OUT) as shown in Figure 21. Low

leakage capacitors in the 10 pF to 500 pF range provide the best

performance. Since FB is internally connected to a high imped-

ance node, any connection to this node should be carefully done

to avoid noise pickup from external sources. The pad connected

to this pin should be as small as possible and long PC board

traces are not recommended. When adding a noise reduction

capacitor, use the following guidelines:

•

Maintain a minimum load current of 1 mA when not in

shutdown

•

For CNR values greater than 500 pF, add a 100 k

Ω series

resistor (RNR).

It is important to note that as CNR increases, the turn-on time

will be delayed. With CNR values greater than 1 nF, this delay

may be on the order of several milliseconds.