OR4E2 datasheet(20/124 Pages) AGERE

20 / 124 page

Lucent Technologies Inc.

Preliminary Data Sheet

December 2000

ORCA Series 4 FPGAs

Programmable Logic Cells (continued)

The PFU memory mode uses all LUTs and latches/FFs

including the ninth FF in its implementation as shown in

Figure 12. The read address is input at the KZ[3:0] and

F5[A:D] inputs where KZ[0] is the LSB and F5[A:D] is

the MSB, and the write address is input on CIN (MSB)

and DIN[7, 5, 3, 1], with DIN[1] being the LSB. Write

data is input on DIN[6, 4, 2, 0], where DIN[6] is the

MSB, and read data is available combinatorially on

F[6, 4, 2, 0] and registered on Q[6, 4, 2, 0] with F[6] and

Q[6] being the MSB. The write enable controlling ports

are input on CE0, CE1, and LSR0. CE1 is the active-

high write enable (CE1 = 1, RAM is write enabled). The

first write port is enabled by CE0. The second write

port is enabled with LSR0. The PFU CLK (CLK0) signal

is used to synchronously write the data. The polarities

of the clock, write enable, and port enables are all pro-

grammable. Write-port enables may be disabled if they

are not to be used.

Data is written to the write data, write address, and

write enable registers on the active edge of the clock,

but data is not written into the RAM until the next clock

edge one-half cycle later. The read port is actually

asynchronous, providing the user with read data very

quickly after setting the read address, but timing is also

provided so that the read port may be treated as fully

synchronous for write then read applications. If the

read and write address lines are tied together (main-

taining MSB to MSB, etc.), then the dual-port RAM

operates as a synchronous single-port RAM. If the

write enable is disabled, and an initial memory contents

are provided at configuration time, the memory acts as

a ROM (the write data and write address ports and

write port enables are not used).

Wider memories can be created by operating two or

more memory mode PFUs in parallel, all with the same

address and control signals, but each with a different

nibble of data. To increase memory word depth above

32, two or more PLCs can be used. Figure 10 shows a

128 x 8 dual-port RAM that is implemented in eight

PLCs. This figure demonstrates data path width expan-

sion by placing two memories in parallel to achieve an

8-bit data path. Depth expansion is applied to achieve

128 words deep using the 32-word deep PFU memo-

ries. In addition to the PFU in each PLC, the SLIC

(described in the next section) in each PLC is used for

read address decodes and 3-state drivers. The 128 x 8

RAM shown could be made to operate as a single-port

RAM by tying (bit-for-bit) the read and write addresses.

To achieve depth expansion, one or two of the write

address bits (generally the MSBs) are routed to the

write port enables as in Figure 10. For 2 bits, the bits

select which 32-word bank of RAM of the four available

from a decode of two WPE inputs is to be written. Simi-

larly, 2 bits of the read address are decoded in the

SLIC and are used to control the 3-state buffers

through which the read data passes. The write data

bus is common, with separate nibbles for width expan-

sion, across all PLCs, and the read data bus is com-

mon (again, with separate nibbles) to all PLCs at the

output of the 3-state buffers.

Figure 13 also shows the capability to provide a read

enable for RAMs/ROMs using the SLIC cell. The read

enable will 3-state the read data bus when inactive,

allowing the write data and read data buses to be tied

together if desired.

OR4E2 データシート(PDF) 20 Page - Agere Systems

OR4E2 データシート(HTML) 20 Page - Agere Systems

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

データシートダウンロード