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WM8731SEDS/RV データシート(PDF) 18 Page - Wolfson Microelectronics plc |
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WM8731SEDS/RV データシート(HTML) 18 Page - Wolfson Microelectronics plc |
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18 / 65 page  WM8731 / WM8731L Production Data w PD, Rev 4.9, October 2012 18 Test Conditions AVDD, HPVDD, DBVDD = 3.3V, AGND = 0V, DCVDD = 1.5V, DGND = 0V, TA = +25 oC, Slave Mode, fs = 48kHz, XTI/MCLK = 256fs unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT ADCDAT propagation delay from BCLK falling edge tDD 0 35 ns MPU INTERFACE TIMING CSB SCLK SDIN t CSL t DHO t DSU t CSH t SCY t SCH t SCL t SCS LSB t CSS Figure 7 Program Register Input Timing - 3-Wire MPU Serial Control Mode Test Conditions AVDD, HPVDD, DBVDD = 3.3V, AGND = 0V, DCVDD = 1.5V, DGND = 0V, TA = +25 oC, Slave Mode, fs = 48kHz, XTI/MCLK = 256fs unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Program Register Input Information SCLK rising edge to CSB rising edge tSCS 60 ns SCLK pulse cycle time tSCY 80 ns SCLK pulse width low tSCL 20 ns SCLK pulse width high tSCH 20 ns SDIN to SCLK set-up time tDSU 20 ns SCLK to SDIN hold time tDHO 20 ns CSB pulse width low tCSL 20 ns CSB pulse width high tCSH 20 ns CSB rising to SCLK rising tCSS 20 ns |
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