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M24C01-W データシート(PDF) 13 Page - STMicroelectronics

部品番号 M24C01-W
部品情報  Enhanced ESD/latch-up protection, More than 40-year data retention
PDF  38 Pages
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メーカー  STMICROELECTRONICS [STMicroelectronics]
ホームページ  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

M24C01-W データシート(HTML) 13 Page - STMicroelectronics

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M24C16, M24C08, M24C04, M24C02, M24C01
Device operation
Doc ID 5067 Rev 17
13/38
Figure 7.
Write mode sequences with WC = 1 (data write inhibited)
3.6
Write operations
Following a Start condition the bus master sends a device select code with the Read/Write
bit (RW) reset to 0. The device acknowledges this, as shown in Figure 8, and waits for an
address byte. The device responds to the address byte with an acknowledge bit, and then
waits for the data byte.
When the bus master generates a Stop condition immediately after a data byte Ack bit (in
the “10th bit” time slot), either at the end of a Byte Write or a Page Write, the internal write
cycle is triggered. A Stop condition at any other time slot does not trigger the internal write
cycle.
After the Stop condition, the tw delay, and the successful completion of a Write operation,
the device internal address counter is automatically incremented, to point to the next byte
address after the last one that was modified. During the internal Write cycle,
Serial Data (SDA) is disabled internally, and the device does not respond to any request.
If the Write Control (WC) input is driven High, the Write instruction is not executed and the
corresponding data bytes are not acknowledged as shown in Figure 7.
Byte Write
Dev select
Byte address
Data in
WC
Page Write
Dev select
Byte address
Data in 1
Data in 2
WC
Data in 3
AI02803d
Page Write
(cont'd)
WC (cont'd)
Data in N
ACK
ACK
NO ACK
R/W
ACK
ACK
NO ACK
NO ACK
R/W
NO ACK
NO ACK



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