ADP5050ACPZ-R7 datasheet(28/60 Pages) AD

部品番号	ADP5050ACPZ-R7

部品情報	5-Channel Integrated Power Solution with Quad Buck Regulators and 200 mA LDO Regulator

PDF	60 Pages

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28 / 60 page

ADP5050

Data Sheet

Rev. 0 | Page 28 of 60

I2C INTERFACE TIMING DIAGRAMS

Figure 59 shows the timing diagram for the I2C write operation.

Figure 60 shows the timing diagram for the I2C read operation.

The subaddress is used to select one of the user registers in the

ADP5050. The ADP5050 sends data to and from the register

specified by the subaddress.

SCL

CHIP ADDRESS

SDA

SUBADDRESS

WRITE DATA

R/W

NOTES

1. MAXIMUM SCL FREQUENCY IS 400kHz.

2. NO RESPONSE TO GENERAL CALLS.

OUTPUT BY PROCESSOR

OUTPUT BY ADP5050

Figure 59. I2C Write to Register

SCL

CHIP ADDRESS

SDA

SUBADDRESS

CHIP ADDRESS

READ DATA

NOTES

1. MAXIMUM SCL FREQUENCY IS 400kHz.

2. NO RESPONSE TO GENERAL CALLS.

OUTPUT BY PROCESSOR

OUTPUT BY ADP5050

R/W

Figure 60. I2C Read from Register

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