MPC875CVR133 datasheet(4/84 Pages) FREESCALE

4 / 84 page

MPC875/MPC870 PowerQUICC™ Hardware Specifications, Rev. 4

Freescale Semiconductor

Features

– ECB, CBC, and counter modes

– 128-, 192-, and 256-bit key lengths

— Message digest execution unit (MDEU)

– SHA with 160- or 256-bit message digest

– MD5 with 128-bit message digest

– HMAC with either algorithm

— Master/slave logic, with DMA

– 32-bit address/32-bit data

– Operation at MPC8xx bus frequency

— Crypto-channel supporting multi-command descriptors

–

Integrated controller managing crypto-execution units

–

Buffer size of 256 bytes for each execution unit, with flow control for large data sizes

•

Interrupts

— Six external interrupt request (IRQ) lines

— Twelve port pins with interrupt capability

— Twenty-three internal interrupt sources

— Programmable priority between SCCs

— Programmable highest priority request

•

Communications processor module (CPM)

— RISC controller

— Communication-specific commands (for example, GRACEFUL STOP TRANSMIT, ENTER HUNT

MODE

, and RESTART TRANSMIT)

— Supports continuous mode transmission and reception on all serial channels

— 8-Kbytes of dual-port RAM

— Several serial DMA (SDMA) channels to support the CPM

— Three parallel I/O registers with open-drain capability

•

On-chip 16

× 16 multiply accumulate controller (MAC)

— One operation per clock (two-clock latency, one-clock blockage)

— MAC operates concurrently with other instructions

— FIR loop—Four clocks per four multiplies

•

Four baud-rate generators

— Independent (can be connected to SCC or SMC)

— Allows changes during operation

— Autobaud support option

•

SCC (serial communication controller)

— Ethernet/IEEE 802.3® standard, supporting full 10-Mbps operation

— HDLC/SDLC

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