OMAP3530ECBBA datasheet(147/264 Pages) TI1

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VIDEO DAC SPECIFICATIONS

OMAP Device

DSS

tv_vref

DIN1[9:0]

vssa_dac

vdda_dac

VideoDAC 1

TVDCT

VideoDAC 2

TVOUT

BUFFER

DIN2[9:0]

TVOUT

BUFFER

TVOUT

BUFFER

tv_vfb1

tv_out1

CBG

tv_out2

tv_vfb2

V_ref

030-018

5.1 Interface Description

OMAP3530/25 Applications Processor

www.ti.com

SPRS507F – FEBRUARY 2008 – REVISED OCTOBER 2009

A dual-display interface equips the OMAP3530/25 processor. This display subsystem provides the

necessary control signals to interface the memory frame buffer directly to the external displays (TV-set).

Two (one per channel) 10-bit current steering DACs are inserted between the DSS and the TV set to

generate the video analog signal. One of the video DACs also includes TV detection and power-down

mode. Figure 5-1 illustrates the OMAP3530/25 DAC architecture. For more information, see the DSS

chapter of the OMAP35x Technical Reference Manual (TRM) [literature number SPRUF98].

Figure 5-1. Video DAC Architecture

The following paragraphs detail the 10-bit DAC interface pinout, static and dynamic specifications, and

noise requirements. The operating conditions and absolute maximum ratings are detailed in Table 5-2 and

Table 5-4.

Table 5-1 summarizes the external pins of the video DAC.

Table 5-1. External Pins of 10-bit Video DAC

PIN NAME

I/O

DESCRIPTION

tv_out1

TV analog output composite

DAC1 video output. An external resistor is connected between this

node and tv_vfb1. The nominal value of ROUT1 is 1650

Ω. Finally,

note that this is the output node that drives the load (75

Ω).

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VIDEO DAC SPECIFICATIONS

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