OMAP3530ECBBA datasheet(150/264 Pages) TI1

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OMAP3530/25 Applications Processor

SPRS507F – FEBRUARY 2008 – REVISED OCTOBER 2009

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(TMIN to TMAX, vdda_dac = 1.8 V, ROUT1/2 = 1650 Ω, RLOAD = 75 Ω, unless otherwise noted)

Table 5-3. Video DAC – Dynamic Electrical Specification

PARAMETER

CONDITIONS/ASSUMPTIONS

MIN

TYP

MAX

UNIT

fCLK

(1)

Output update rate

Equal to input clock frequency

MHz

Clock jitter

rms clock jitter required in order to assure

10-bit accuracy

Attenuation at 5.1 MHz

Corner frequency for signal

0.1

0.5

1.5

Attenuation at 54 MHz(1)

Image frequency

tST

Output settling time

Time from the start of the output transition to

output within

± 1 LSB of final value.

tRout

Output rise time

Measured from 10% to 90% of full-scale

transition

tFout

Output fall time

Measured from 10% to 90% of full-scale

transition

Signal bandwidth

MHz

Differential gain(2)

1.5%

Differential phase(2)

deg.

SFDR

Within bandwidth

fCLK = 54 MHz, fOUT = 1 MHz

SNR

Signal-to-noise ratio

fCLK = 54 MHz, fOUT = 1 MHz

55(3)

1 kHz to 6 MHz bandwidth

PSRR

Power supply rejection ratio

Up to 6 MHz

20(4)

Crosstalk

Between the two video

–50

–40

channels

(1)

For internal input clock information, For more information, see the DSS chapter of the OMAP35x Technical Reference Manual (TRM)

[literature number SPRUF98].

(2)

The differential gain and phase value is for dc coupling. Note that there is degradation for the ac coupling.

(3)

The SNR value is for dc coupling. Note that there is a 6-dB degradation for ac coupling.

(4)

The PSSR value is for dc coupling. Note that there is a 10-dB degradation for ac coupling.

VIDEO DAC SPECIFICATIONS

150

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