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STM32F103RCT7 データシート(PDF) 95 Page - STMicroelectronics

部品番号 STM32F103RCT7
部品情報  High-density performance line ARM-based 32-bit MCU with 256 to 512KB Flash, USB, CAN, 11 timers, 3 ADCs, 13 communication interfaces
PDF  130 Pages
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メーカー  STMICROELECTRONICS [STMicroelectronics]
ホームページ  http://www.st.com
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STM32F103RCT7 データシート(HTML) 95 Page - STMicroelectronics

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STM32F103xC, STM32F103xD, STM32F103xE
Electrical characteristics
Doc ID 14611 Rev 8
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I2S - SPI characteristics
Unless otherwise specified, the parameters given in Table 53 for SPI or in Table 54 for I2S
are derived from tests performed under ambient temperature, fPCLKx frequency and VDD
supply voltage conditions summarized in Table 10.
Refer to Section 5.3.14: I/O port characteristics for more details on the input/output alternate
function characteristics (NSS, SCK, MOSI, MISO for SPI and WS, CK, SD for I2S).
Table 53.
SPI characteristics
Symbol
Parameter
Conditions
Min
Max
Unit
fSCK
1/tc(SCK)
SPI clock frequency
Master mode
18
MHz
Slave mode
18
tr(SCK)
tf(SCK)
SPI clock rise and fall
time
Capacitive load: C = 30 pF
8
ns
DuCy(SCK)
SPI slave input clock duty
cycle
Slave mode
30
70
%
tsu(NSS)
(1)
1.
Based on characterization, not tested in production.
NSS setup time
Slave mode
4tPCLK
ns
th(NSS)
(1)
NSS hold time
Slave mode
2tPCLK
tw(SCKH)
(1)
tw(SCKL)
(1)
SCK high and low time
Master mode, fPCLK = 36 MHz,
presc = 4
50
60
tsu(MI)
(1)
tsu(SI)
(1)
Data input setup time
Master mode
5
Slave mode
5
th(MI)
(1)
Data input hold time
Master mode
5
th(SI)
(1)
Slave mode
4
ta(SO)
(1)(2)
2.
Min time is for the minimum time to drive the output and the max time is for the maximum time to validate
the data.
Data output access time
Slave mode, fPCLK = 20 MHz
0
3tPCLK
tdis(SO)
(1)(3)
3.
Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put
the data in Hi-Z
Data output disable time
Slave mode
2
10
tv(SO)
(1)
Data output valid time
Slave mode (after enable edge)
25
tv(MO)
(1)
Data output valid time
Master mode (after enable edge)
5
th(SO)
(1)
Data output hold time
Slave mode (after enable edge)
15
th(MO)
(1)
Master mode (after enable edge)
2



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