V

BATT

GND

MCLK_IN

LDO

Switch/

Decoder

EN

V

CC

V

LDO

CLK_OUT1

CLK_REQ1

CLK_OUT2

CLK_REQ2

EN

V

CC

CDC3RL02

SCHS371 – NOVEMBER 2009

www.ti.com

ORDERING INFORMATION

ORDERABLE PART NUMBER

–40°C to 85°C

NanoStar™ WCSP – YFP

Tape and reel

CDC3RL02YFPR

_ _ _ 4 L _

(1)

Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.

(2)

For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI

website at www.ti.com.

(3)

YFP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following

character to designate the wafer fab/assembly site. Pin 1 identifier indicates solder-bump composition (1 = SnPb,

● = Pb-free).

TERMINAL FUNCTIONS

NO.

NAME

I/O

DESCRIPTION

A1

I

Input to internal LDO

A2

CLK_OUT1

O

Clock output 1

B1

O

1.8 V I/O supply for CDC3RL02 and external TCXO

B2

CLK_REQ1

I

Clock request from peripheral 2

C1

MCLK_IN

I

Master clock input

C2

CLK_REQ2

I

Clock request from peripheral 1

D1

GND

–

Ground

D2

CLK_OUT2

O

Clock output 2

Table 2. FUNCTION TABLE

INPUTS

OUTPUTS

CLK_REQ1

CLK_REQ2

MCLK_IN

CLK_OUT1

CLK_OUT2

L

L

X

L

L

L

H

CLK

L

CLK

H

L

CLK

CLK

L

H

H

CLK

CLK

CLK

LOGIC DIAGRAM

2

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Product Folder Link(s): CDC3RL02