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ST7570TR データシート(PDF) 22 Page - STMicroelectronics

部品番号 ST7570TR
部品情報  S-FSK power line networking system-on-chip
PDF  26 Pages
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メーカー  STMICROELECTRONICS [STMicroelectronics]
ホームページ  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

ST7570TR データシート(HTML) 22 Page - STMicroelectronics

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Physical layer
ST7570
22/26
Doc ID 17526 Rev 2
9.3
Frame structure at physical level
The frame at physical level is compliant with the IEC61334-5-1 and is composed of 45 bytes
(360 bits) as follows:
2 byte preamble (PRE) (AAAAh);
2 byte start subframe delimiter (SSD) (54C7h);
38 byte physical service data unit (P_sdu);
3 byte for pause or alarm;
The bytes are sent from the most significant byte (MSB) to the least significant byte (LSB).
Bits within the byte are packed with the same order (msb to lsb).
Figure 14.
Physical frame format
9.4
Frame timing and time-slot synchronization
The IEC61334-5-1 protocol specifies a master-slave network with time-division medium
access: in order to properly communicate, all the nodes belonging to a network must share
the same “slot synchronization”.
The time division is fixed through the use of time-slots, corresponding to a physical frame
length of 45 bytes (i.e. 360 bits) with a total duration equal to:
15 mains cycles, at the 1200 bps operating speed (at 50 Hz);
7.5 mains cycles, at the 2400 bps operating speed (at 50 Hz).
The slot synchronization is first achieved by the master (i.e. ST7570 modem in 'Client'
mode) setting the time-slot starting at the mains zero-crossing instant. The frames
transmitted by the master will enable the slot synchronization of all other slave nodes (i.e.
ST7570 working in 'Server' mode): the reception of the sequence composed by PRE and
SSD will allow all the 'Server' nodes aligning their time-slots to the Client's time-slot.



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