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STM8S003K3 データシート(PDF) 13 Page - STMicroelectronics |
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STM8S003K3 データシート(HTML) 13 Page - STMicroelectronics |
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13 / 100 page  • Startup clock: After reset, the microcontroller restarts by default with an internal 2 MHz clock (HSI/8). The prescaler ratio and clock source can be changed by the application program as soon as the code execution starts. • Clock security system (CSS): This feature can be enabled by software. If an HSE clock failure occurs, the internal RC (16 MHz/8) is automatically selected by the CSS and an interrupt can optionally be generated. • Configurable main clock output (CCO): This outputs an external clock for use by the application. Table 2: Peripheral clock gating bit assignments in CLK_PCKENR1/2 registers Peripheral clock Bit Peripheral clock Bit Peripheral clock Bit Peripheral clock Bit ADC PCKEN23 Reserved PCKEN27 UART1 PCKEN13 TIM1 PCKEN17 AWU PCKEN22 Reserved PCKEN26 Reserved PCKEN12 Reserved PCKEN16 Reserved PCKEN21 Reserved PCKEN25 SPI PCKEN11 TIM2 PCKEN15 Reserved PCKEN20 Reserved PCKEN24 I 2C PCKEN10 TIM4 PCKEN14 Power management 4.6 For efficent power management, the application can be put in one of four different low-power modes. You can configure each mode to obtain the best compromise between lowest power consumption, fastest start-up time and available wakeup sources. • Wait mode: In this mode, the CPU is stopped, but peripherals are kept running. The wakeup is performed by an internal or external interrupt or reset. • Active halt mode with regulator on: In this mode, the CPU and peripheral clocks are stopped. An internal wakeup is generated at programmable intervals by the auto wake up unit (AWU). The main voltage regulator is kept powered on, so current consumption is higher than in active halt mode with regulator off, but the wakeup time is faster. Wakeup is triggered by the internal AWU interrupt, external interrupt or reset. • Active halt mode with regulator off: This mode is the same as active halt with regulator on, except that the main voltage regulator is powered off, so the wake up time is slower. • Halt mode: In this mode the microcontroller uses the least power. The CPU and peripheral clocks are stopped, the main voltage regulator is powered off. Wakeup is triggered by external event or reset. Watchdog timers 4.7 The watchdog system is based on two independent timers providing maximum security to the applications. Activation of the watchdog timers is controlled by option bytes or by software. Once activated, the watchdogs cannot be disabled by the user program without performing a reset. 13/100 DocID018576 Rev 3 Product overview STM8S003K3 STM8S003F3 |
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