AD7839

–5–

REV. 0

PIN FUNCTION DESCRIPTIONS

Pin

No.

Mnemonic

Description

1

DUTGND_AB

applied to this pin.

2, 44, 43,

DAC Outputs.

41, 37, 35,

34, 32

4, 3

Reference Inputs for DACs A and B. These reference voltages are referred to GND.

Positive Analog Power Supply; +15 V

± 5%.

Negative Analog Power Supply; –15 V

± 5%.

7

LDAC

Load DAC Logic Input (active low). When this logic input is taken low the contents of the

input registers are transferred to their respective DAC registers.

LDAC can be tied perma-

nently low enabling the outputs to be updated on the rising edge of

WR.

10, 9, 8

A0, A1, A2

Address inputs. A0, A1 and A2 are decoded to select one of the eight input registers for a

data transfer.

11

CS

Level-Triggered Chip Select Input (active low). The device is selected when this input is low.

12

WR

Level-Triggered Write Input (active low), used in conjunction with

CS to write data to the

AD7839 input registers. Data is latched into the selected input register on the rising edge of

WR.

13

Logic Power Supply; +5 V

± 5%.

14

GND

Ground.

15–27

DB0 . . DB12

Parallel Data Inputs. The AD7839 can accept a straight 13-bit parallel word on DB0 to DB12

where DB12 is the MSB and DB0 is the LSB.

28

CLR

Asynchronous Clear Input (level sensitive, active low). When this input is low, all analog

outputs are switched to the externally set potential on the relevant DUTGND pin. The con-

tents of input registers and DAC registers A to H are not affected when the

CLR pin is taken

low. When

CLR is brought back high, the DAC outputs revert to their original outputs as

determined by the data in their DAC registers.

30, 31

Reference Inputs for DACs G and H. These reference voltages are referred to GND.

33

DUTGND_GH

applied to this pin.

36

DUTGND_EF

applied to this pin.

39

Reference Inputs for DACs C, D, E and F. These reference voltages are referred to GND.

40

42

DUTGND_CD

applied to this pin.