AD7940 datasheet(16/28 Pages) AD

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AD7686

Rev. B | Page 16 of 28

The AD7686 powers down automatically at the end of each

conversion phase and, therefore, the power scales linearly with

the sampling rate, as shown in Figure 31. This makes the part

ideal for low sampling rates (even a few Hz) and low battery-

powered applications.

SAMPLING RATE (SPS)

1000

100

10000

0.1

0.01

0.001

100

1000

10000

100000

1000000

VIO

VDD = 5V

Figure 31. Operating Currents vs. Sampling Rate

SUPPLYING THE ADC FROM THE REFERENCE

For simplified applications, the AD7686, with its low operating

current, can be supplied directly using the reference circuit

shown in Figure 32. The reference line can be driven by either:

•

The system power supply directly.

•

A reference voltage with enough current output capability,

such as the ADR43x.

•

A reference buffer, such as the AD8031, which can also

filter the system power supply, as shown in Figure 32.

AD8031

AD7686

VIO

REF

VDD

10µF

1µF

10Ω

10kΩ

1µF

1OPTIONAL REFERENCE BUFFER AND FILTER.

Figure 32. Example of Application Circuit

DIGITAL INTERFACE

Though the AD7686 has a reduced number of pins, it offers

flexibility in its serial interface modes.

The AD7686, when in CS mode, is compatible with SPI, QSPI,

digital hosts, and DSPs, such as Blackfin® ADSP-BF53x or

ADSP-219x. This interface can use either 3-wire or 4-wire. A

3-wire interface using the CNV, SCK, and SDO signals

minimizes wiring connections useful, for instance, in isolated

applications. A 4-wire interface using the SDI, CNV, SCK, and

SDO signals allows CNV, which initiates the conversions, to be

independent of the readback timing (SDI). This is useful in low

jitter sampling or simultaneous sampling applications.

The AD7686, when in chain mode, provides a daisy-chain

feature using the SDI input for cascading multiple ADCs on a

single data line similar to a shift register.

The mode in which the part operates depends on the SDI level

when the CNV rising edge occurs. The CS mode is selected if

SDI is high, and the chain mode is selected if SDI is low. The

SDI hold time is such that when SDI and CNV are connected

together, the chain mode is always selected.

In either mode, the AD7686 offers the flexibility to optionally

force a start bit in front of the data bits. This start bit can be

used as a busy signal indicator to interrupt the digital host and

trigger the data reading. Otherwise, without a busy indicator,

the user must timeout the maximum conversion time prior to

readback.

The busy indicator feature is enabled as follows:

• In CS mode, if CNV or SDI is low when the ADC conversion

ends (see Figure 36 and Figure 40).

• In chain mode, if SCK is high during the CNV rising edge

(see Figure 44).

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