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ADXL362BCCZ-R2 データシート(PDF) 33 Page - Analog Devices

部品番号 ADXL362BCCZ-R2
部品情報  Micropower, 3-Axis, 2g/4g/8g Digital Output MEMS Accelerometer
PDF  44 Pages
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メーカー  AD [Analog Devices]
ホームページ  http://www.analog.com
Logo AD - Analog Devices

ADXL362BCCZ-R2 データシート(HTML) 33 Page - Analog Devices

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Data Sheet
ADXL362
Rev. B | Page 33 of 44
FILTER CONTROL REGISTER
Address: 0x2C, Reset: 0x13, Name: FILTER_CTL
Table 17. Bit Descriptions for FILTER_CTL
Bits
Bit Name
Settings
Description
Reset
Access
[7:6]
RANGE
Measurement Range Selection.
0x0
RW
00
±2 g (reset default)
01
±4 g
1X
±8 g
5
RES
Reserved.
0x0
RW
4
HALF_BW
Halved Bandwidth. Additional information is provided in the Antialiasing section.
0x1
1 = the bandwidth of the antialiasing filters is set to ¼ the output data rate (ODR) for
more conservative filtering.
0 = the bandwidth of the filters is set to ½ the ODR for a wider bandwidth.
3
EXT_SAMPLE
External Sampling Trigger. 1 = the INT2 pin is used for external conversion timing
control. Refer to the Using Synchronized Data Sampling section for more
information.
0x0
RW
[2:0]
ODR
Output Data Rate. Selects ODR and configures internal filters to a bandwidth of ½ or
¼ the selected ODR, depending on the HALF_BW bit setting.
0x3
RW
000
12.5 Hz
001
25 Hz
010
50 Hz
011
100 Hz (reset default)
100
200 Hz
101…111
400 Hz



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