AD7984 datasheet(19/24 Pages) AD

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Data Sheet

AD7960

Rev. 0 | Page 19 of 24

DIGITAL INTERFACE

CONVERSION CONTROL

All analog-to-digital conversions are controlled by the CNV±

signal. This signal can be applied in the form of a CNV+/CNV−

LVDS signal, or it can be applied in the form of a 1.8 V CMOS

logic signal to the CNV+ pin when CNV− is grounded. The

conversion is initiated by the rising edge of the CNV± signal.

After the AD7960 is powered up, the first conversion result

generated is valid. The key beneficial feature of the AD7960 is

that the user can return to the acquisition phase before the end

of the conversion.

The two methods for acquiring the digital data output of the

AD7960 via the LVDS interface are described in the Echoed

Clock Interface Mode and Self Clocked Mode sections.

Echoed Clock Interface Mode

The digital operation of the AD7960 in echoed clock interface

mode is shown in Figure 35. This interface mode, requiring only a

shift register on the digital host, can be used with many digital

hosts (such as FPGA, shift register, and microprocessor). It requires

three LVDS pairs (D±, CLK±, and DCO±) between each AD7960

and the digital host.

The clock DCO± is a buffered copy of CLK± and is synchronous

to the data, D±, which is updated on the falling edge of DCO±

(tD). By maintaining good propagation delay matching between

D± and DCO± through the board and the digital host, DCO± can

be used to latch D± with good timing margin for the shift register.

Conversions are initiated by a rising edge of the CNV± pulse.

The CNV± pulse must be returned low (≤tCNVH maximum) for

valid operation. After a conversion begins, it continues until

completion. Additional CNV± pulses are ignored during the

conversion phase. After tMSB elapses, the host begins to burst the

CLK±. Note that tMSB is the maximum time for the MSB of the

new conversion result. Use tMSB as the gating device for CLK±.

The echoed clock, DCO±, and the data, D±, are driven in phase

with D± being updated on the falling edge of DCO±; the host

uses the rising edge of DCO± to capture D±. The only require-

ment is that the 18 CLK± pulses finish before tCLKL of the next

conversion phase elapses, or the data is lost. After all 18 bits are

read, up to tMSB, D± and DCO± are driven to 0. Set CLK± to idle

low between CLK± bursts.

Figure 35. Echoed Clock Interface Mode Timing Diagram

CLK+

tCYC

tACQ

CNV+

118

tCNVH

tCLKL

DCO+

D+

SAMPLE N

SAMPLE N + 1

D–

D17

D16

CLK–

CNV–

DCO–

N – 1

ACQUISITION

tDCO

tCLK

tMSB

N – 1

D17

N + 1

D16

N + 1

D15

N + 1

tCLKD

ACQUISITION

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