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DSPIC30F2020AT-30EMM データシート(PDF) 91 Page - Microchip Technology |
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DSPIC30F2020AT-30EMM データシート(HTML) 91 Page - Microchip Technology |
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91 / 286 page  © 2006 Microchip Technology Inc. Preliminary DS70178C-page 89 dsPIC30F1010/202X 8.4 Timer Interrupt The 16-bit timer has the ability to generate an interrupt on period match. When the timer count matches the period register, the T1IF bit is asserted and an interrupt will be generated, if enabled. The T1IF bit must be cleared in software. The timer interrupt flag T1IF is located in the IFS0 control register in the Interrupt Controller. When the Gated Time Accumulation mode is enabled, an interrupt will also be generated on the falling edge of the gate signal (at the end of the accumulation cycle). Enabling an interrupt is accomplished via the respec- tive timer interrupt enable bit, T1IE. The timer interrupt enable bit is located in the IEC0 control register in the Interrupt Controller. |
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