PCF8564AU datasheet(21/48 Pages) NXP

21 / 48 page

PCF8564A

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Product data sheet

Rev. 3 — 26 August 2013

21 of 48

NXP Semiconductors

PCF8564A

Real time clock and calendar

Characteristics of the I2C-bus

The I2C-bus is for bidirectional, two-line communication between different ICs or modules.

The two lines are a Serial DAta line (SDA) and a Serial CLock line (SCL). Both lines must

be connected to a positive supply via a pull-up resistor. Data transfer may be initiated only

when the bus is not busy.

9.1 Bit transfer

One data bit is transferred during each clock pulse. The data on the SDA line must remain

stable during the HIGH period of the clock pulse as changes in the data line at this time

will be interpreted as a control signal (see Figure 11).

9.2 START and STOP conditions

Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW

transition of the data line, while the clock is HIGH, is defined as the START condition (S).

A LOW-to-HIGH transition of the data line, while the clock is HIGH, is defined as the

STOP condition (P), see Figure 12.

9.3 System configuration

A device generating a message is a transmitter, a device receiving a message is the

receiver. The device that controls the message is the master; and the devices which are

controlled by the master are the slaves (see Figure 13).

Fig 11. Bit transfer

Fig 12. Definition of START and STOP conditions

PCF8564AU データシート(PDF) 21 Page - NXP Semiconductors