データシートサーチシステム
  Japanese  ▼
ALLDATASHEET.JP

X  

AFS600-FGG484ES データシート(PDF) 49 Page - Microsemi Corporation

部品番号 AFS600-FGG484ES
部品情報  Fusion Family of Mixed Signal FPGAs
PDF  334 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
メーカー  MICROSEMI [Microsemi Corporation]
ホームページ  http://www.microsemi.com
Logo MICROSEMI - Microsemi Corporation

AFS600-FGG484ES データシート(HTML) 49 Page - Microsemi Corporation

Back Button AFS600-FGG484ES Datasheet HTML 45Page - Microsemi Corporation AFS600-FGG484ES Datasheet HTML 46Page - Microsemi Corporation AFS600-FGG484ES Datasheet HTML 47Page - Microsemi Corporation AFS600-FGG484ES Datasheet HTML 48Page - Microsemi Corporation AFS600-FGG484ES Datasheet HTML 49Page - Microsemi Corporation AFS600-FGG484ES Datasheet HTML 50Page - Microsemi Corporation AFS600-FGG484ES Datasheet HTML 51Page - Microsemi Corporation AFS600-FGG484ES Datasheet HTML 52Page - Microsemi Corporation AFS600-FGG484ES Datasheet HTML 53Page - Microsemi Corporation Next Button
Zoom Inzoom in Zoom Outzoom out
 49 / 334 page
background image
Fusion Family of Mixed Signal FPGAs
Revision 4
2-33
Real-Time Counter System
The RTC system enables Fusion devices to support standby and sleep modes of operation to reduce
power consumption in many applications.
•
Sleep mode, typical 10 µA
•
Standby mode (RTC running), typical 3 mA with 20 MHz
The RTC system is composed of five cores:
•
RTC sub-block inside Analog Block (AB)
•
Voltage Regulator and Power System Monitor (VRPSM)
•
Crystal oscillator (XTLOSC); refer to the "Crystal Oscillator" section in the Fusion Clock
Resources chapter of the Fusion FPGA Fabric User’s Guide for more detail.
•
Crystal clock; does not require instantiation in RTL
•
1.5 V voltage regulator; does not require instantiation in RTL
All cores are powered by 3.3 V supplies, so the RTC system is operational without a 1.5 V supply during
standby mode. Figure 2-27 shows their connection.
Notes:
1. Signals are hardwired internally and do not exist in the macro core.
2. User is only required to instantiate the VRPSM macro if the user wishes to specify PUPO behavior of the voltage regulator
to be different from the default, or employ user logic to shut the voltage regulator off.
Figure 2-27 • Real-Time Counter System (not all the signals are shown for the AB macro)
VRPU
PTBASE1
PTEM1
PUB
VRINITSTATE
RTCPSMMATCH
FPGAGOOD
PUCORE
VREN1
VREN1
VRPSM
1.5 Voltage Regulator
RTCXTLSEL
RTCMATCH
RTCPSMMATCH
XTLOSC
Real-Time Counter
XTAL1
XTAL2
CLKOUT
RTC_MODE[1:0]
SELMODE
RTCCLK
External
Pass
Transistor
2N2222
3.3 V
Power-Up/-Down
Toggle Control
Switch
1.5 V
TRST1
External Pin
Internal Pin
Can Be Route
to PLL
RTCXTLMODE[1:0]
Cores do not require any
RTL instantiation
Cores require RTL instantiation2
Sub-block in cores does not
require additional RTL instantiation
XTL
XTL1
Crystal Clock
MODE[1:0]
FPGA_EN1
AB



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


データシート ダウンロード

Go To PDF Page


リンク URL



ALLDATASHEETはお客様のビジネスに役立ちますか?  [ DONATE ] 

Alldatasheetは   |   広告   |   お問い合わせ   |   プライバシーポリシー   |   データシートへのリンク    |   リンク交換   |   メーカーリスト
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com