AD977/AD977A

–13–

REV. D

EXTERNAL CONTINUOUS CLOCK DATA READ DURING

CONVERSION WITH SYNC OUTPUT GENERATED

Figure 9 illustrates the method by which data from conversion

“n-1” can be read during conversion “n” while using a continu-

ous external clock with the generation of a SYNC output. What

permits the generation of a SYNC output is a transition of

DATACLK while either

CS is high or while both CS and R/C

are low.

With a continuous clock the

CS pin cannot be tied low as it

could be with a discontinuous clock. Use of a continuous clock

while a conversion is occurring can increase the DNL and

Transition Noise of the AD977/AD977A.

In Figure 9 a conversion is initiated by taking R/

C low with CS

held low. While this condition exists a transition of DATACLK,

clock pulse #0, will enable the generation of a SYNC pulse.

Less then 83 ns after R/

C is taken low the BUSY output will go

low to indicate that the conversion process has began. Figure 9

shows R/

C then going high and after a delay of greater than

SYNC output. The SYNC output will appear approximately

50 ns after this rising edge and will be valid on the falling edge

of clock pulse #1 and the rising edge of clock pulse #2. The

MSB will be valid approximately 40 ns after the rising edge of

clock pulse #2 and can be latched off either the falling edge of

clock pulse #2 or the rising edge of clock pulse #3. The LSB

will be valid on the falling edge of clock pulse #17 and the rising

edge of clock pulse #18. Approximately 40 ns after the rising

edge of clock pulse #18, the DATA output pin will reflect the

state of the TAG input pin during the rising edge of clock

pulse #2.

For both the AD977 and the AD977A the data should be

clocked out during the 1st half of

BUSY so as not to degrade

conversion performance. For the AD977 this requires use of a

4.8 MHz DATACLK or greater with data being read out as

soon as the conversion process begins. For the AD977A it

requires use of a 10 MHz DATACLK or greater.

CS

BUSY

R/C

EXT

DATACLK

BIT 15

(MSB)

1

DATA

SYNC

03

BIT 0

(LSB)

TAG 0

TAG 1

TAG 0

TAG

2

18

TAG 2

TAG 1

TAG 16

TAG 17

TAG 18

TAG 19

Figure 9. Conversion and Read Timing for Reading Previous Conversion Results During a Conversion Using An External

Continuous Data Clock (EXT/

INT Set to Logic High)