MPC8245EC datasheet(7/68 Pages) FREESCALE

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MPC8245 Integrated Processor Hardware Specifications, Rev. 10

Freescale Semiconductor

Electrical and Thermal Characteristics

PLL supply voltage—peripheral logic

AVDD2

1.8/1.9/2.0 V ±

4, 7, 12

2.0/2.1 V ±

5, 7, 12

PCI reference

LVDD

5.0 ± 5%

2, 10, 11

3.3 ± 0.3

3, 10, 11

Input voltage

PCI inputs

Vin

0 to 3.6 or 5.75

2, 3

All other inputs

0 to 3.6

Die-junction temperature

0 to 105

°C

Notes:

1. These are the recommended and tested operating conditions. Proper device operation outside of these conditions is not

guaranteed.

2. PCI pins are designed to withstand LVDD + 5% V DC when LVDD is connected to a 5.0-V DC power supply.

3. PCI pins are designed to withstand LVDD + 0.5 V DC when LVDD is connected to a 3.3-V DC power supply.

4. The voltage supply value of 1.8/1.9/2.0 V ± 100 mV applies to parts marked as having a maximum CPU speed of 266 and

300 MHz. See Table 7. For each chosen nominal value (1.8/1.9/2.0 V) the supply voltage should not exceed ± 100 mV of

the nominal value.

5. The voltage supply value of 2.0/2.1 V ± 100 m V applies to parts marked as having a maximum CPU speed of 333 and 350

MHz. See Table 7. For each chosen nominal value (2.0/2.1 V) the supply voltage should not exceed ± 100 mV of the nominal

value.

Cautions:

6. Input voltage (Vin) must not be greater than the supply voltage (VDD/AVDD/AVDD2) by more than 2.5 V at all times, including

during power-on reset. Input voltage (Vin) must not be greater than GVDD/OVDD by more than 0.6 V at all times, including

during power-on reset.

7. OVDD must not exceed VDD/AVDD/AVDD2 by more than 1.8 V at any time, including during power-on reset. This limit may

be exceeded for a maximum of 20 ms during power-on reset and power-down sequences.

8. VDD/AVDD/AVDD2 must not exceed OVDD by more than 0.6 V at any time, including during power-on reset. This limit may

be exceeded for a maximum of 20 ms during power-on reset and power-down sequences.

9. GVDD must not exceed VDD/AVDD/AVDD2 by more than 1.8 V at any time, including during power-on reset. This limit may

be exceeded for a maximum of 20 ms during power-on reset and power-down sequences.

10.LVDD must not exceed VDD/AVDD/AVDD2 by more than 5.4 V at any time, including during power-on reset. This limit may be

exceeded for a maximum of 20 ms during power-on reset and power-down sequences.

11. LVDD must not exceed OVDD by more than 3.0 V at any time, including during power-on reset. This limit may be exceeded

for a maximum of 20 ms during power-on reset and power-down sequences.

12.This voltage is the input to the filter discussed in Section 7.1, “PLL Power Supply Filtering,” and not necessarily the voltage

at the AVDD pin, which may be reduced from VDD by the filter.

Table 2. Recommended Operating Conditions1 (continued)

Characteristic

Symbol

Recommended

Value

Unit

Notes

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