AD7910ARMZ2 datasheet(21/24 Pages) AD

21 / 24 page

AD7910/AD7920

Rev. C | Page 21 of 24

For example, the ADSP-2111 has a master clock frequency of

16 MHz. If the SCLKDIV register is loaded with the value 3, an

SCLK of 2 MHz is obtained and eight master clock periods

elapse for every one SCLK period. If the timer registers are

loaded with the value 803, 100.5 SCLKs occur between

interrupts and subsequently between transmit instructions. This

situation results in nonequidistant sampling as the transmit

instruction is occurring on an SCLK edge. If the number of

SCLKs between interrupts is a whole integer figure of N,

equidistant sampling is implemented by the DSP.

AD7910/AD7920 TO DSP563xx INTERFACE

The diagram in Figure 27 shows how the AD7910/AD7920 can

be connected to the synchronous serial interface (SSI)

(synchronous serial interface) of the DSP563xx family of DSPs

from Motorola. The SSI is operated in synchronous and normal

mode (SYN = 1 and MOD = 0 in Control Register B, CRB) with

internally generated word frame sync for both Tx and Rx (Bit

FSL1 = 0 and Bit FSL0 = 0 in the CRB). Set the word length in

the Control Register A (CRA) to 16 by setting Bits WL2 = 0,

WL1 = 1, and WL0 = 0 for the AD7920. This DSP does not

offer the option for a 14-bit word length, so the AD7910 word

length is set to 16 bits like the AD7920. For the AD7910, the

conversion process uses 16 SCLK cycles, with the last two clock

periods clocking out two trailing zeros to fill the 16-bit word.

To implement the power-down mode on the AD7910/AD7920,

the word length can be changed to eight bits by setting Bits

WL2 = 0, WL1 = 0, and WL0 = 0 in CRA. The FSP bit in the

CRB register can be set to 1, which means the frame goes low

and a conversion starts. Likewise, by means of Bits SCD2,

SCKD, and SHFD in the CRB register, it is established that Pin

SC2 (the frame sync signal) and SCK in the serial port is

configured as outputs and the MSB is shifted first.

To summarize:

MOD = 0

SYN = 1

WL2, WL1, WL0 Depend on the Word Length

FSL1 = 0, FSL0 = 0

FSP = 1, Negative Frame Sync

SCD2 = 1

SCKD = 1

SHFD = 0

It should be noted that for signal processing applications, it is

imperative that the frame synchronization signal from the

DSP563xx provides equidistant sampling.

AD7910/AD7920*

SDATA

SCLK

DSP563xx*

SCK

SRD

SC2

*ADDITIONAL PINS OMITTED FOR CLARITY

Figure 27. Interfacing to the DSP563xx

AD7910ARMZ2 データシート(PDF) 21 Page - Analog Devices

AD7910ARMZ2 データシート(HTML) 21 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

データシートダウンロード