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AD9920ABBCZ データシート(PDF) 5 Page - Analog Devices |
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AD9920ABBCZ データシート(HTML) 5 Page - Analog Devices |
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5 / 112 page  AD9920A Rev. B | Page 5 of 112 DIGITAL SPECIFICATIONS IOVDD = 1.6 V to 3.6 V, RGVDD = HVDD1 and HVDD2 = 2.7 V to 3.6 V, CL = 20 pF, TMIN to TMAX, unless otherwise noted. Table 2. Parameter Symbol Test Conditions/Comments Min Typ Max Unit LOGIC INPUTS (IOVDD) High Level Input Voltage VIH VDD − 0.6 V Low Level Input Voltage VIL 0.6 V High Level Input Current IIH 10 μA Low Level Input Current IIL 10 μA Input Capacitance CIN 10 pF LOGIC OUTPUTS (IOVDD, DRVDD) High Level Output Voltage VOH IOH = 2 mA VDD − 0.5 V Low Level Output Voltage VOL IOL = 2 mA 0.5 V RG and H-DRIVER OUTPUTS (HVDD1, HVDD2, and RGVDD) High Level Output Voltage VOH Maximum current VDD − 0.5 V Low Level Output Voltage VOL Maximum current 0.5 V Maximum H1 to H8 Output Current Programmable 30 mA Maximum HL and RG Output Current Programmable 17 mA Maximum Load Capacitance Each output 60 pF CLI INPUT With CLO oscillator disabled High Level Input Voltage VIHCLI CLIVDD/2 + 0.5 V Low Level Input Voltage VILCLI CLIVDD/2 − 0.5 V ANALOG SPECIFICATIONS AVDD = 1.8 V, fCLI = 40.5 MHz, typical timing specifications, TMIN to TMAX, unless otherwise noted. Table 3. Parameter Test Conditions/Comments Min Typ Max Unit CDS1 DC Restore AVDD − 0.5 V 1.21 1.3 1.44 V Allowable CCD Reset Transient Limit is the lower of AVDD + 0.3 V or 2.2 V 0.5 0.8 V CDS Gain Accuracy VGA gain = 6.3 dB (Code 15, default value) −3 dB CDS Gain −3.1 −2.6 −2.1 dB 0 dB CDS Gain −0.6 −0.1 +0.4 dB +3 dB CDS Gain 2.7 3.2 3.7 dB +6 dB CDS Gain 5.2 5.7 6.2 dB Maximum Input Range Before Saturation −3 dB CDS Gain 1.4 V p-p 0 dB CDS Gain 1.0 V p-p +3 dB CDS Gain 0.7 V p-p +6 dB CDS Gain 0.5 V p-p Allowable OB Pixel Amplitude1 0 dB CDS Gain (Default) −100 +200 mV +6 dB CDS Gain −50 +100 mV VARIABLE GAIN AMPLIFIER (VGA) Gain Control Resolution 1024 Steps Gain Monotonicity Guaranteed Gain Range Low Gain VGA Code 15, default 6.3 dB Maximum Gain VGA Code 1023 42.4 dB |
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