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ADM1069ASTZ データシート(PDF) 6 Page - Analog Devices

部品番号 ADM1069ASTZ
部品情報  Super Sequencer with Margining Control
PDF  32 Pages
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メーカー  AD [Analog Devices]
ホームページ  http://www.analog.com
Logo AD - Analog Devices

ADM1069ASTZ データシート(HTML) 6 Page - Analog Devices

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ADM1069
Rev. C | Page 6 of 32
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
Standard (Digital Output) Mode (PDO1 to PDO8)
VOH
2.4
V
VPU (pull-up to VDDCAP or VPx) = 2.7 V, IOH = 0.5 mA
4.5
V
VPU to VPx = 6.0 V, IOH = 0 mA
VPU − 0.3
V
VPU ≤ 2.7 V, IOH = 0.5 mA
VOL
0
0.50
V
IOL = 20 mA
IOL2
20
mA
Maximum sink current per PDOx pin
ISINK2
60
mA
Maximum total sink for all PDOx pins
RPULL-UP
16
20
29
kΩ
Internal pull-up
ISOURCE (VPx)2
2
mA
Current load on any VPx pull-ups, that is, total
source current available through any number of
PDO pull-up switches configured onto any one
VPx pin
Three-State Output Leakage Current
10
μA
VPDO = 14.4 V
Oscillator Frequency
90
100
110
kHz
All on-chip time delays derived from this clock
DIGITAL INPUTS (VXx, A0, A1)
Input High Voltage, VIH
2.0
V
Maximum VIN = 5.5 V
Input Low Voltage, VIL
0.8
V
Maximum VIN = 5.5 V
Input High Current, IIH
−1
μA
VIN = 5.5 V
Input Low Current, IIL
1
μA
VIN = 0 V
Input Capacitance
5
pF
Programmable Pull-Down Current, IPULL-DOWN
20
μA
VDDCAP = 4.75 V, TA = 25°C, if known logic state
is required
SERIAL BUS DIGITAL INPUTS (SDA, SCL)
Input High Voltage, VIH
2.0
V
Input Low Voltage, VIL
0.8
V
Output Low Voltage, VOL2
0.4
V
IOUT = −3.0 mA
SERIAL BUS TIMING3
Clock Frequency, fSCLK
400
kHz
Bus Free Time, tBUF
1.3
μs
Start Setup Time, tSU;STA
0.6
μs
Stop Setup Time, tSU;STO
0.6
μs
Start Hold Time, tHD;STA
0.6
μs
SCL Low Time, tLOW
1.3
μs
SCL High Time, tHIGH
0.6
μs
SCL, SDA Rise Time, tR
300
ns
SCL, SDA Fall Time, tF
300
ns
Data Setup Time, tSU;DAT
100
ns
Data Hold Time, tHD;DAT
5
ns
Input Low Current, IIL
1
μA
VIN = 0 V
SEQUENCING ENGINE TIMING
State Change Time
10
μs
1 At least one of the VH, VPx pins must be ≥ 3.0 V to maintain the device supply on VDDCAP.
2 Specification is not production tested but is supported by characterization data at initial product release.
3 Timing specifications are guaranteed by design and supported by characterization data.



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