AD7986

Rev. B | Page 19 of 28

CS MODE, 3-WIRE WITHOUT BUSY INDICATOR

This mode is usually used when a single AD7986 is connected

to an SPI-compatible digital host. The connection diagram is

shown in Figure 25, and the corresponding timing is given in

Figure 26.

With SDI tied to VIO, a rising edge on CNV initiates a conversion,

selects the CS mode, and forces SDO to high impedance. Once

a conversion is initiated, it continues until completion irrespective

of the state of CNV. This can be useful, for instance, to bring

CNV low to select other SPI devices, such as analog multiplexers;

however, CNV must be returned high before the minimum

conversion time elapses and then held high for the maximum

possible conversion time to avoid the generation of the busy

signal indicator. When the conversion is complete, the AD7986

enters the acquisition phase and powers down. When CNV

goes low, the MSB is output onto SDO. The remaining data bits

are clocked by subsequent SCK falling edges. The data is valid on

both SCK edges. Although the rising edge can be used to

capture the data, a digital host using the SCK falling edge allows

a faster reading rate, provided that it has an acceptable hold

(whichever occurs first), SDO returns to high impedance.

AD7986

SDI

SDO

CNV

SCK

CONVERT

DATA IN

CLK

DIGITAL HOST

VIO

Figure 25. CS Mode, 3-Wire Without Busy Indicator Connection Diagram (SDI High)

ACQUISITION (n)

ACQUISITION

(n + 1)

ACQUISITION

(n - 1)

1

2

BEGIN DATA (n – 1)

CONVERSION (n)

END DATA (n – 1)

SCK

CNV

SDO

16

17

CONVERSION (n – 1)

END DATA (n – 2)

0

(I/O QUIET

TIME)

(I/O QUIET

TIME)

18

16

17

18

1

17

16

15

2

0

1

2

SDI = 1

>

(QUIET

TIME)

Figure 26. CS Mode, 3-Wire Without Busy Indicator Serial Interface Timing (SDI High)