MPC8548ECHXATHA datasheet(39/151 Pages) FREESCALE

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MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 9

Freescale Semiconductor

Enhanced Three-Speed Ethernet (eTSEC)

Figure 18 shows the RMII transmit AC timing diagram.

Figure 18. RMII Transmit AC Timing Diagram

8.2.7.2

RMII Receive AC Timing Specifications

TSECn_TX_CLK to RMII data TXD[1:0], TX_EN delay

tRMTDX

1.0

—

10.0

Note:

1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for

inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMTKHDX symbolizes MII transmit

timing (MT) for the time tMTX clock reference (K) going high (H) until data outputs (D) are invalid (X). Note that, in general,

the clock reference symbol representation is based on two to three letters representing the clock of a particular functional.

For example, the subscript of tMTX represents the MII(M) transmit (TX) clock. For rise and fall times, the latter convention is

used with the appropriate letter: R (rise) or F (fall).

Table 35. RMII Receive AC Timing Specifications

Parameter/Condition

Symbol1

Min

Typ

Max

Unit

TSECn_TX_CLK clock period

tRMR

15.0

20.0

25.0

TSECn_TX_CLK duty cycle

tRMRH

TSECn_TX_CLK peak-to-peak jitter

tRMRJ

——

250

Rise time TSECn_TX_CLK(20%–80%)

tRMRR

1.0

—

2.0

Fall time TSECn_TX_CLK (80%–20%)

tRMRF

1.0

—

2.0

RXD[1:0], CRS_DV, RX_ER setup time to REF_CLK rising edge

tRMRDV

4.0

—

RXD[1:0], CRS_DV, RX_ER hold time to REF_CLK rising edge

tRMRDX

2.0

—

Note:

1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for

inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMRDVKH symbolizes MII receive

timing (MR) with respect to the time data input signals (D) reach the valid state (V) relative to the tMRX clock reference (K)

going to the high (H) state or setup time. Also, tMRDXKL symbolizes MII receive timing (GR) with respect to the time data input

signals (D) went invalid (X) relative to the tMRX clock reference (K) going to the low (L) state or hold time. Note that, in general,

the clock reference symbol representation is based on three letters representing the clock of a particular functional. For

example, the subscript of tMRX represents the MII (M) receive (RX) clock. For rise and fall times, the latter convention is used

with the appropriate letter: R (rise) or F (fall).

Table 34. RMII Transmit AC Timing Specifications (continued)

Parameter/Condition

Symbol1

Min

Typ

Max

Unit

TSECn_TX_CLK

TXD[1:0]

tRMTDX

tRMT

tRMTH

tRMTR

tRMTF

TX_EN

TX_ER

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