AD9754ARURL7 datasheet(15/24 Pages) AD

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AD9754

–15–

REV. A

SINGLE-ENDED UNBUFFERED VOLTAGE OUTPUT

Figure 30 shows the AD9754 configured to provide a unipolar

output range of approximately 0 V to +0.5 V for a doubly termi-

nated 50

Ω cable since the nominal full-scale current, I

OUTFS, of

20 mA flows through the equivalent RLOAD of 25

Ω. In this case,

RLOAD represents the equivalent load resistance seen by IOUTA

or IOUTB. The unused output (IOUTA or IOUTB) can be

connected to ACOM directly or via a matching RLOAD. Different

values of IOUTFS and RLOAD can be selected as long as the posi-

tive compliance range is adhered to. One additional consider-

ation in this mode is the integral nonlinearity (INL) as discussed

in the Analog Output section of this data sheet. For optimum

INL performance, the single-ended, buffered voltage output

configuration is suggested.

AD9754

IOUTA

IOUTB 21

VOUTA = 0 TO +0.5V

IOUTFS = 20mA

Figure 30. 0 V to +0.5 V Unbuffered Voltage Output

SINGLE-ENDED BUFFERED VOLTAGE OUTPUT

CONFIGURATION

Figure 31 shows a buffered single-ended output configuration in

which the op amp U1 performs an I-V conversion on the AD9754

output current. U1 maintains IOUTA (or IOUTB) at a virtual

ground, thus minimizing the nonlinear output impedance effect

on the DAC’s INL performance as discussed in the Analog

Output section. Although this single-ended configuration typi-

cally provides the best dc linearity performance, its ac distortion

performance at higher DAC update rates may be limited by

U1’s slewing capabilities. U1 provides a negative unipolar

output voltage and its full-scale output voltage is simply the

product of RFB and IOUTFS. The full-scale output should be set

within U1’s voltage output swing capabilities by scaling IOUTFS

and/or RFB. An improvement in ac distortion performance may

result with a reduced IOUTFS since the signal current U1 will be

required to sink will be subsequently reduced.

AD9754

IOUTA

IOUTB 21

COPT

200

VOUT = IOUTFS

RFB

IOUTFS = 10mA

RFB

200

Figure 31. Unipolar Buffered Voltage Output

POWER AND GROUNDING CONSIDERATIONS, POWER

SUPPLY REJECTION

Many applications seek high speed and high performance under

less than ideal operating conditions. In these circuits, the imple-

mentation and construction of the printed circuit board design

is as important as the circuit design. Proper RF techniques must

be used for device selection, placement and routing as well as

power supply bypassing and grounding to ensure optimum

performance. Figures 39-44 illustrate the recommended printed

circuit board ground, power and signal plane layouts which are

implemented on the AD9754 evaluation board.

One factor that can measurably affect system performance is the

ability of the DAC output to reject dc variations or ac noise

superimposed on the analog or digital dc power distribution

(i.e., AVDD, DVDD). This is referred to as Power Supply

Rejection Ratio (PSRR). For dc variations of the power supply,

the resulting performance of the DAC directly corresponds to a

gain error associated with the DAC’s full-scale current, IOUTFS.

AC noise on the dc supplies is common in applications where

the power distribution is generated by a switching power supply.

Typically, switching power supply noise will occur over the

spectrum from tens of kHz to several MHz. PSRR vs. frequency

of the AD9754 AVDD supply, over this frequency range, is

given in Figure 32.

FREQUENCY – MHz

1.0

0.5

0.75

0.26

Figure 32. Power Supply Rejection Ratio of AD9754

Note that the units in Figure 32 are given in units of (amps out)/

(volts in). Noise on the analog power supply has the effect of

modulating the internal switches, and therefore the output

current. The voltage noise on the dc power, therefore, will be

added in a nonlinear manner to the desired IOUT. Due to the

relative different sizes of these switches, PSRR is very code

dependent. This can produce a mixing effect which can modu-

late low frequency power supply noise to higher frequencies.

Worst case PSRR for either one of the differential DAC outputs

will occur when the full-scale current is directed towards that

output. As a result, the PSRR measurement in Figure 32 repre-

sents a worst case condition in which the digital inputs remain

static and the full-scale output current of 20 mA is directed to

the DAC output being measured.

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