APW8700 datasheet(21/26 Pages) ANPEC

21 / 26 page

Rev. A.1 - Jun., 2011

APW8700

www.anpec.com.tw

Application Information (Cont.)

Layout Consideration (Cont.)

The signals going through theses traces have both

high dv/dt and high di/dt with high peak charging and

discharging current. The traces from the gate drivers

to the MOSFETs (UGATEx and LGATEx) should be short

and wide.

Place the source of the high-side MOSFET and the

drain of the low-side MOSFET as close as possible.

Minimizing the impedance with wide layout plane be-

tween the two pads reduces the voltage bounce of

the node. In addition, the large layout plane between

the drain of the MOSFETs (V

IN and PHASEx nodes)

can get better heat sinking.

For experiment result of accurate current sensing, the

current sensing components are suggested to place

close to the inductor part. To avoid the noise

interference, the current sensing trace should be away

from the noisy switching nodes.

Decoupling capacitors, the resistor-divider, and boot

capacitor should be close to their pins. (For example,

place the decoupling ceramic capacitor close to the

drain of the high-side MOSFET as close as possible).

The input bulk capacitors should be close to the drain

of the high-side MOSFET, and the output bulk capaci-

tors should be close to the loads. The input capaci-

tor’s ground should be close to the grounds of the

output capacitors and low-side MOSFET.

Locate the resistor-divider close to the FB pin to mini-

mize the high impedance trace. In addition, FB pin

traces can’t be close to the switching signal traces

(UGATEx, LGATEx, BOOTx, and PHASEx).

•

Keep the switching nodes (UGATEx, LGATEx, BOOTx,

and PHASEx) away from sensitive small signal nodes

since these nodes are fast moving signals. Therefore,

keep traces to these nodes as short as possible and

there should be no other weak signal traces in paral-

lel with theses traces on any layer.

Figure 11. Layout Guidelines

•

BOOT1

PHASE1

UGATE1

LGATE1

IN1=VIN

APW8700

IN2 =VIN

BOOT2

PHASE2

UGATE2

LGATE2

OUT

CSN

CSP

RS1

RS2

RCSN

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