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データシートサーチシステム |
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データシートサーチシステム |
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AX2000 データシート(PDF) 83 Page - Microsemi Corporation |
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AX2000 データシート(HTML) 83 Page - Microsemi Corporation |
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83 / 262 page  Axcelerator Family FPGAs Re vi s i on 18 2 - 69 Table 2-77 • AX500 Routed Array Clock Networks Worst-Case Commercial Conditions VCCA = 1.425 V, VCCI = 3.0 V, TJ = 70°C –2 Speed –1 Speed Std Speed Parameter Description Min. Max. Min. Max. Min. Max. Units Routed Array Clock Networks tRCKL Input Low to High 2.31 2.63 3.09 ns tRCKH Input High to Low 2.44 2.78 3.27 ns tRPWH Minimum Pulse Width High 0.57 0.64 0.75 ns tRPWL Minimum Pulse Width Low 0.52 0.59 0.69 ns tRCKSW Maximum Skew 0.35 0.39 0.46 ns tRP Minimum Period 1.15 1.31 1.54 ns tRMAX Maximum Frequency 870 763 649 MHz Table 2-78 • AX1000 Routed Array Clock Networks Worst-Case Commercial Conditions VCCA = 1.425 V, VCCI = 3.0 V, TJ = 70°C –2 Speed –1 Speed Std Speed Parameter Description Min. Max. Min. Max. Min. Max. Units Routed Array Clock Networks tRCKL Input Low to High 3.08 3.50 4.12 ns tRCKH Input High to Low 3.13 3.56 4.19 ns tRPWH Minimum Pulse Width High 0.57 0.64 0.75 ns tRPWL Minimum Pulse Width Low 0.52 0.59 0.69 ns tRCKSW Maximum Skew 0.35 0.39 0.46 ns tRP Minimum Period 1.15 1.31 1.54 ns tRMAX Maximum Frequency 870 763 649 MHz Table 2-79 • AX2000 Routed Array Clock Networks Worst-Case Commercial Conditions VCCA = 1.425 V, VCCI = 3.0 V, TJ = 70°C –2 Speed –1 Speed Std Speed Parameter Description Min. Max. Min. Max. Min. Max. Units Routed Array Clock Networks tRCKL Input Low to High 3.08 3.50 4.12 ns tRCKH Input High to Low 3.13 3.56 4.19 ns tRPWH Minimum Pulse Width High 0.57 0.64 0.75 ns tRPWL Minimum Pulse Width Low 0.52 0.59 0.69 ns tRCKSW Maximum Skew 0.35 0.39 0.46 ns tRP Minimum Period 1.15 1.31 1.54 ns tRMAX Maximum Frequency 870 763 649 MHz |
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