AD6640AST datasheet(14/24 Pages) AD

14 / 24 page

AD6640

–14–

REV. A

AD6640 output data is latched using 74LCX574 (U3, U4)

latches following 348

Ω series resistors. The resistors limit the

current that would otherwise flow due to the digital output slew

rate. The resistor value was chosen to represent a time constant

of ~25% of the data rate at 65 MHz. This reduces slew rate

while not appreciably distorting the data waveform. Data is

latched in a pipeline configuration; a rising edge generates the

new AD6640 data sample, latches the previous data at the con-

verter output, and strobes the external data register over J3.

Note that power and ground must be applied to J3 to power the

digital logic section of the evaluation board.

Table I. AD6640ST/PCB Bill of Material

Item

Quantity

Reference

Description

+5 VA, GND

Banana Jack

211C7–C9, C11–C17, C19

Ceramic Chip Capacitor 0805, 0.1

µF

C4, C6

Tantalum Chip Capacitor 10

µF

40-Lead Double Row Male Header

J1, J2, J4

BNC Coaxial PCB Connector

Surface Mount Resistor 1206, 348

Ω

725R2–R14, R20–R25, R30–R35

Surface Mount Resistor 1206, 348

Ω

R15

Surface Mount Resistor 1206, 100

Ω

R16

Surface Mount Resistor 1206, 270

Ω

T1, T2

Surface Mount Transformer Mini-Circuits T4–1T, 1:4 Ratio

Clock Oscillator (Optional)

DUT

AD6640AST 12-Bit–65 MSPS A/D Converter

U3, U4

74LCX574 Octal Latch

74LVQ00 Quad Two Input NAND Gate

C1, C18

Ceramic Chip Capacitor 0508, 0.01

µF Low Inductance

C2, C3

Ceramic Chip Capacitor 0508, 0.1

µF Low Inductance

CR1, CR2

1N2810 Schottky Diode

DIGITAL WIDEBAND RECEIVERS

Introduction

Several key technologies are now being introduced that may

forever alter the vision of radio. Figure 25 shows the typical dual

conversion superheterodyne receiver. The signal picked up by

the antenna is mixed down to an intermediate frequency (IF)

using a mixer with a variable local oscillator (LO); the variable

LO is used to “tune-in” the desired signal. This first IF is

mixed down to a second IF using another mixer stage and a

fixed LO. Demodulation takes place at the second or third IF

using either analog or digital techniques.

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