AMD

15

Am7992B

SWITCHING CHARACTERISTICS (continued)

preamble is applied to Receive

Notes:

1. Tested but to values in excess of limits. Test accuracy not sufficient to allow screening guardbands.

.

3. Not tested.

4. Test done by monitoring output functionally.

5. Receive, Collision and Transmit functions are inactive: X1 driven by 20 MHz.

6. Not more than one output should be shorted at a time. Duration of the short circuit test should not exceed one second.

7. TCLK changes state on X1 rising edge, but initial state of TCLK is not defined. When TENA is High, TX data is

Manchester encoded on the falling edge of X1 after the rising edge of TCLK.

8. Assumes 50 pF capacitance loading on RCLK and RX.

9. Test is done only for last BIT = 1, which is worst case.

10. Test done from 0.8 V of falling to 2.0 V of rising edge.

.

12. Measured from 50% point of X1 driving the input in production test.

No.

Parameters

Description

Test Conditions

Min

Max

Unit

Transmitter Specification

24

TCLK LOW Time

(Note 11)

45

ns

25

TCLK HIGH Time

45

ns

26

TCLK Rise Time

8

ns

27

TCLK Rise Time

8

ns

28

TX and TENA Setup Time to TCLK

5

ns

29

TX and TENA Hold Time to TCLK

5

ns

30

Transmit

± Output, (Bit Cell Center to Edge)

49.5

50.5

ns

31

TCLK HIGH to Transmit

± Output

100

ns

32

Transmit

± Output Rise Time

4

ns

33

Transmit

± Output Fall Time

4

ns

34

X1 to TCLK Propagation Delay for HIGH

5

18

ns

35

X1 to TCLK Propagation Delay for LOW

5

18

ns

36

Clock Acquisition Jitter Tolerance

16

21.5

ns

37

Jitter Tolerance After 50 Bit Times

19

24.4

ns

(Note 1)

20% – 80%

(Notes 7 & 12)