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AM79C985JC データシート(PDF) 37 Page - Advanced Micro Devices |
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AM79C985JC データシート(HTML) 37 Page - Advanced Micro Devices |
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37 / 48 page  Am79C985 37 PRELIMINARY SWITCHING CHARACTERISTICS Parameter Symbol Parameter Description Test Conditions Min Max Unit Clock and Reset Timing tCLK CLK Clock Period 49.995 50.005 ns tCLKH CLK Clock High 20 30 ns tCLKL CLK Clock Low 20 30 ns tCLKR CLK Rise Time – 10 ns tCLKF CLK Fall Time – 10 ns tPRST Reset Pulse Width after Power On 150 – µs tRST Reset Pulse Width 4 – µs tRSTSET Reset HIGH Setup Time with respect to CLK 15 – ns tRSTHLD Reset LOW Hold Time 0 – ns tXRS AMODE, SELI0, CRS_I, and SI_D Setup Time to Rising Edge of RST 0 – ns tXRH AMODE,SELI0, CRS_I and SI_D Hold Time from Rising Edge of RST 400 – ns AUI Port Timing tDOTD CLK Rising Edge to DO Toggle – 30 ns tDOTR DO+, DO– Rise Time (10% to 90%) – 7.0 ns tDOTF DO+, DO– Fall Time (90% to 10%) – 7.0 ns tDORM DO+, DO– Rise and Fall Time Mismatch – 1.0 ns tDOETD DO ± End of Transmission 275 375 ns tPWODI DI Pulse Width Accept/Reject Threshold |VIN|>|VASQ| (Note 2) 15 45 ns tPWKDI DI Pulse Width Not to Turn-off Internal Carrier Sense |VIN|>|VASQ| (Note 3) 136 200 ns tPWOCI CI Pulse Width Accept/Reject Threshold |VIN|>|VASQ| (Note 4) 10 26 ns tPWKCI CI Pulse Width Not to Turn-off Threshold |VIN|>|VASQ| (Note 5) 75 160 ns tCITR CI Rise Time (In Reverse Mode) – 7.0 ns tCITF CI Fall Time (In Reverse Mode) – 7.0 ns tCIRM CI+, CI– Rise and Fall Time Mismatch (AUI in Reverse Mode) – 1.0 ns Expansion Bus Timing tCLKHRL CLK HIGH to SELO Driven LOW CL = 50 pF 15 30 ns tCLKHRH CLK HIGH to SELO Driven HIGH CL = 50 pF 15 30 ns tCLKHDR CLK HIGH to DAT/JAM Driven CL = 100 pF 14 30 ns tCLKHDZ CLK HIGH to DAT/JAM Not Driven CL = 100 pF 14 30 ns tDJSET DAT/JAM Setup Time to CLK 10 – ns tDJHOLD DAT/JAM Hold Time from CLK 9 – ns tCASET COL/ACK Setup Time to CLK 10 – ns tCAHLD COL/ACK Hold Time from CLK 9 – ns tSCLKHLD SI, SCLK Hold Time 50 – ns |
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